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path: root/src/map/if/if.h
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* Experiments with the mapper.Alan Mishchenko2022-06-231-0/+2
* Adding switch to dsd_match to skip small functions.Alan Mishchenko2022-05-181-1/+1
* Adding switch to &if to consider special type of 6-input cuts.Alan Mishchenko2019-09-261-0/+4
* Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to pri...Alan Mishchenko2019-09-191-0/+1
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-051-2/+2
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-0/+3
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-221-0/+2
* Maintenance and updates.Alan Mishchenko2017-09-201-2/+4
* Maintenance and updates.Alan Mishchenko2017-09-181-0/+1
* Adding truth table occurrence counters for 'if -c'.Alan Mishchenko2016-08-081-0/+1
* Enabled delay computation for the cut output using cut inputs.Alan Mishchenko2016-08-081-0/+1
* Infrastructure for using the results of exact SAT-based synthesis during mapp...Alan Mishchenko2016-07-291-0/+3
* Adding option to rehash AIG after mapping.Alan Mishchenko2016-04-271-0/+1
* Compiler warnings.Alan Mishchenko2015-10-211-2/+2
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-161-0/+1
* Experiments with mapping plus small changes.Alan Mishchenko2015-08-231-0/+1
* Small changes to enable collecting results using &ps -D file.Alan Mishchenko2015-07-091-0/+1
* Supporting AND-gate cuts in 'if' and '&if'Alan Mishchenko2015-06-211-4/+7
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-3/+7
* Adding new mapping feature.Alan Mishchenko2014-12-111-0/+2
* Detection of threshold functions.Alan Mishchenko2014-10-081-0/+1
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-1/+11
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-0/+2
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-1/+3
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-0/+2
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-0/+4
* Improving DSD manager.Alan Mishchenko2014-09-181-0/+1
* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-1/+1
* Improvements to Boolean matching.Alan Mishchenko2014-09-171-0/+1
* Adding new command &sopb for resource-aware SOP balancing.Alan Mishchenko2014-07-211-0/+1
* Correcting switching activity computation.Alan Mishchenko2014-06-051-0/+1
* Added optimization for average rather than maximum delay.Alan Mishchenko2014-04-191-3/+3
* Improvements to DSD balancing.Alan Mishchenko2014-04-191-0/+3
* Fix SOP balancing.Alan Mishchenko2014-04-191-1/+1
* Improvements in technology mapping.Alan Mishchenko2014-04-171-2/+1
* Changes in the LUT mapper data-structures.Alan Mishchenko2014-04-141-2/+4
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-111-0/+1
* Improvements to DSD in technology mapping.Alan Mishchenko2014-04-111-2/+3
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-111-0/+2
* Correcting internal check.Alan Mishchenko2014-04-111-1/+1
* Removed obsolete code for sequential mapping.Alan Mishchenko2014-04-111-4/+4
* Improvements to DSD in technology mapping.Alan Mishchenko2014-04-111-3/+4
* Implementation of DSD balancing.Alan Mishchenko2014-04-061-1/+1
* Improvement in SOP balancing.Alan Mishchenko2014-04-061-25/+7
* Preparing new implementation of SOP/DSD balancing in 'if' mapper.Alan Mishchenko2014-04-051-4/+11
* Preparing new implementation of SOP/DSD balancing in 'if' mapper.Alan Mishchenko2014-04-051-0/+3
* Tuning LUT mapping to work while saving the best network.Alan Mishchenko2014-04-041-1/+1
* Improvements to technology mapping.Alan Mishchenko2014-04-031-3/+4
* Improvements to technology mapping.Alan Mishchenko2014-04-031-0/+5
* Improvements to technology mapping.Alan Mishchenko2014-04-031-1/+4
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