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path: root/src/map/if/ifDsd.c
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* Compiler warnings.Alan Mishchenko2017-07-221-1/+1
* Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...Alan Mishchenko2016-01-301-1/+1
* Moving BDD-based threshold function detection to the BDD part of the code.Alan Mishchenko2015-10-161-0/+8
* Two fixes in 'dsd_filter'.Alan Mishchenko2015-10-071-1/+1
* Threshold logic checking code by Augusto Neutzling and Jody Matos.Alan Mishchenko2015-09-231-3/+6
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-47/+87
* New assertions and bug fix in DSD balancing.Alan Mishchenko2015-01-271-5/+8
* Small changes.Alan Mishchenko2014-10-081-0/+2
* Compiler warnings.Alan Mishchenko2014-10-081-0/+2
* Detection of threshold functions.Alan Mishchenko2014-10-081-0/+73
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-2/+9
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-7/+37
* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
* Synchronizing packages.Alan Mishchenko2014-09-201-2/+2
* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-1/+12
* Updating DSD balance to handle XOR gate as having the same delay as AND gate.Alan Mishchenko2014-09-191-4/+5
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-5/+21
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-2/+3
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-6/+20
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-4/+16
* Improving DSD manager.Alan Mishchenko2014-09-181-0/+68
* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-3/+219
* Improvements to Boolean matching.Alan Mishchenko2014-09-171-0/+65
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-041-0/+69
* Profiling code for SOP/DSD/LMS balancing.Alan Mishchenko2014-08-021-0/+21
* Improvements to DSD balancing.Alan Mishchenko2014-04-191-1/+1
* Improvements to DSD balancing.Alan Mishchenko2014-04-191-11/+78
* Changes in the LUT mapper data-structures.Alan Mishchenko2014-04-141-2/+2
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-131-1/+5
* New feature to optimize delay during mapping.Alan Mishchenko2014-04-111-6/+8
* Correcting internal check.Alan Mishchenko2014-04-111-29/+38
* Improvements to DSD in technology mapping.Alan Mishchenko2014-04-111-6/+6
* Implementation of DSD balancing.Alan Mishchenko2014-04-061-160/+61
* Improvement in SOP balancing.Alan Mishchenko2014-04-061-7/+12
* Preparing new implementation of SOP/DSD balancing in 'if' mapper.Alan Mishchenko2014-04-051-4/+261
* Preparing new implementation of SOP/DSD balancing in 'if' mapper.Alan Mishchenko2014-04-051-0/+22
* Improvements to technology mapping.Alan Mishchenko2014-04-031-1/+1
* Improvements to technology mapping.Alan Mishchenko2014-04-031-24/+17
* Improvements to technology mapping.Alan Mishchenko2014-04-031-2/+3
* Improvements to DSD manager.Alan Mishchenko2014-04-021-113/+113
* Improvements to DSD manager.Alan Mishchenko2014-04-021-136/+226
* Bug fix in the DSD manager writing and reading.Alan Mishchenko2014-03-311-4/+6
* Experiments with cut caching.Alan Mishchenko2014-03-201-1/+1
* Improvements to print-outs.Alan Mishchenko2014-03-121-1/+3
* Improvements to print-outs.Alan Mishchenko2014-03-111-2/+19
* Improvements to print-outs.Alan Mishchenko2014-03-101-0/+66
* Changes to LUT mappers.Alan Mishchenko2014-03-091-0/+7
* Changes to LUT mappers.Alan Mishchenko2014-03-091-6/+4
* Changes to LUT mappers.Alan Mishchenko2014-03-081-19/+29
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