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path: root/src/map/if/ifTune.c
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* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
* Bug fix in programmable cell parser and minor tuning.Alan Mishchenko2015-07-081-1/+2
* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
* Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.Alan Mishchenko2015-05-151-2/+7
* Making sure 0-input LUTs are supported by the DSD matching code.Alan Mishchenko2015-05-141-5/+5
* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-14/+128
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-2/+2
* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-1/+2
* Compiler warnings.Alan Mishchenko2014-10-081-1/+1
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-7/+78
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-0/+9
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-1/+1
* Updating DSD balance to handle XOR gate as having the same delay as AND gate.Alan Mishchenko2014-09-191-1/+1
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-28/+77
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-61/+434
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-0/+2
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+29
* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-41/+33
* Improvements to Boolean matching.Alan Mishchenko2014-09-171-60/+125
* New choice computation.Alan Mishchenko2014-09-161-9/+9
* Improvements to Boolean matching.Alan Mishchenko2014-09-161-201/+554
* Changes to LUT mappers.Alan Mishchenko2014-03-091-18/+243
* Experiments with stuck-at fault testing.Alan Mishchenko2014-03-091-6/+62
* Changes to LUT mappers.Alan Mishchenko2014-03-081-0/+117
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