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path: root/src/map/if/ifTune.c
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* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-211-2/+2
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* Bug fix in programmable cell parser and minor tuning.Alan Mishchenko2015-07-081-1/+2
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* C++ compiler typecast problem.Alan Mishchenko2015-07-081-1/+1
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* Bug fix in 'dsd_tune' when processing cells with 0-input LUTs.Alan Mishchenko2015-05-151-2/+7
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* Making sure 0-input LUTs are supported by the DSD matching code.Alan Mishchenko2015-05-141-5/+5
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* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
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* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
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* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-14/+128
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* Fixed a typo in variable names.Alan Mishchenko2015-02-071-2/+2
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* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-1/+2
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* Compiler warnings.Alan Mishchenko2014-10-081-1/+1
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* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-7/+78
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* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-0/+9
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* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-1/+1
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* Updating DSD balance to handle XOR gate as having the same delay as AND gate.Alan Mishchenko2014-09-191-1/+1
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* Improvements to Boolean matching.Alan Mishchenko2014-09-191-28/+77
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* Improvements to Boolean matching.Alan Mishchenko2014-09-191-61/+434
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* Improvements to Boolean matching.Alan Mishchenko2014-09-181-0/+2
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* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+29
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* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-41/+33
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* Improvements to Boolean matching.Alan Mishchenko2014-09-171-60/+125
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* New choice computation.Alan Mishchenko2014-09-161-9/+9
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* Improvements to Boolean matching.Alan Mishchenko2014-09-161-201/+554
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* Changes to LUT mappers.Alan Mishchenko2014-03-091-18/+243
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* Experiments with stuck-at fault testing.Alan Mishchenko2014-03-091-6/+62
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* Changes to LUT mappers.Alan Mishchenko2014-03-081-0/+117