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* Corner-case bug-fix in library preprocessor for standard-cell mapping.Alan Mishchenko2017-02-051-2/+2
* Equivalent fault detection code.Alan Mishchenko2016-11-093-0/+5
* New feature for area minimization in standard cell mapping.Alan Mishchenko2016-05-191-0/+5
* Factoring out library preprocessing code in &nf and putting it elsewhere.Alan Mishchenko2016-05-163-0/+59
* Added switch 'read_genlib -n' to anonymize Genlib library.Alan Mishchenko2016-05-163-9/+139
* Adding API to convert Genlib into a simple Liberty.Alan Mishchenko2016-03-112-1/+2
* Disabling formula cleaner to avoid problems with reading GENLIB on some libra...Alan Mishchenko2016-02-211-1/+2
* Bug fix in liberty parser and change suggested by Clifford.Alan Mishchenko2016-02-071-1/+15
* GENLIB parsing bug, which led to a crash.Alan Mishchenko2016-02-061-1/+4
* Consolidating timing manager Scl_Con_t and propagating changes.Alan Mishchenko2016-01-072-6/+5
* Migrating to using 32-bit timing representation in &nf.Alan Mishchenko2016-01-052-16/+16
* Migrating back to using 'float' in area-flow computation in &nf.Alan Mishchenko2016-01-052-7/+9
* Corner-case bug in 'read_profile'.Alan Mishchenko2015-12-221-1/+1
* Adding code to support gate profiles.Alan Mishchenko2015-12-143-30/+71
* Adding code to support gate profiles.Alan Mishchenko2015-12-074-1/+50
* Adding commands to read/write/print gate profiles.Alan Mishchenko2015-12-055-8/+250
* Extending and improving timing manager.Alan Mishchenko2015-11-084-1/+43
* Extending and improving timing manager.Alan Mishchenko2015-11-081-0/+2
* Extending and improving timing manager.Alan Mishchenko2015-11-082-0/+3
* Experiments with precomputation and matching.Alan Mishchenko2015-10-272-0/+2
* Extending library handling to 8 inputs.Alan Mishchenko2015-10-252-1/+61
* Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.Alan Mishchenko2015-10-233-16/+38
* Changes for delay-oriented computation.Alan Mishchenko2015-10-232-2/+4
* Experiments with precomputation and matching.Alan Mishchenko2015-10-152-0/+2
* Experiments with precomputation and matching.Alan Mishchenko2015-10-124-15/+31
* Several bug-fixed related to synthesis, library handling, and timimg info.Alan Mishchenko2015-09-231-2/+4
* Updating Mio to use int instead of float.Alan Mishchenko2015-08-312-2/+192
* Important bug fixes in standard-cell library handling and mapper &nf.Alan Mishchenko2015-08-281-9/+27
* Improving the criteria to select representative gates in 'map' with floating-...Alan Mishchenko2015-04-251-47/+60
* Adding platform-independent (alphabetic) way of sorting Genlib gates and sele...Alan Mishchenko2015-04-172-20/+56
* Adding APIs to retrieve NOR/OR gates from the library.Alan Mishchenko2015-04-144-4/+15
* Getting default AND-node delay from Genlib library.Alan Mishchenko2015-04-062-0/+2
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-9/+9
* Major rehash of the CBA code.Alan Mishchenko2015-01-312-0/+21
* Integrating barrier buffers.Alan Mishchenko2014-12-081-0/+8
* Recommended changes for portability.Alan Mishchenko2014-10-121-1/+1
* Suggested patch for type-punned warningsAlan Mishchenko2014-10-101-3/+6
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-1/+1
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-261-0/+145
* Generating abstraction of standard cell library.Alan Mishchenko2014-07-256-10/+163
* Bug fix in technology mapper.Alan Mishchenko2013-11-241-4/+13
* Several changes to allow Liberty files without delay info.Alan Mishchenko2013-11-211-0/+1
* Improvements to buffering and sizing.Alan Mishchenko2013-10-131-1/+1
* Integrating synthesis into the new BMC engine.Alan Mishchenko2013-10-021-4/+3
* Bug fixes in the library processing,.Alan Mishchenko2013-10-021-6/+10
* Unifying standard cell library representations.Alan Mishchenko2013-09-173-5/+39
* Infrastructure to support full Liberty format and unitification of library re...Alan Mishchenko2013-09-153-3/+5
* Improved gate-sizing.Alan Mishchenko2013-07-292-0/+10
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-242-47/+69
* Small changes to the printout in timing analysis.Alan Mishchenko2013-07-191-1/+1
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