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iCE40/abc
yosys-experimental
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mio
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Author
Age
Files
Lines
*
Compiler warnings.
Alan Mishchenko
2020-05-03
1
-1
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+0
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Adding dumping of genlib library in Verilog.
Alan Mishchenko
2020-05-03
2
-30
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+30
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Adding dumping of genlib library in Verilog.
Alan Mishchenko
2020-05-03
1
-1
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+1
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*
Adding dumping of genlib library in Verilog.
Alan Mishchenko
2020-05-03
4
-7
/
+110
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*
Fixing some warnings by adding cast from 'int' to 'size_t' in memset, ↵
Alan Mishchenko
2019-03-05
2
-5
/
+5
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memcpy, etc.
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Updates and bug fixes.
Alan Mishchenko
2017-10-04
3
-11
/
+19
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*
Maintenance and updates.
Alan Mishchenko
2017-09-24
3
-0
/
+54
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*
Maintenance and updates.
Alan Mishchenko
2017-09-18
3
-0
/
+55
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*
Experiments with new network data-structure.
Alan Mishchenko
2017-03-20
2
-0
/
+2
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*
Experiments with new network data-structure.
Alan Mishchenko
2017-03-19
1
-1
/
+1
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Corner-case bug-fix in library preprocessor for standard-cell mapping.
Alan Mishchenko
2017-02-05
1
-2
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+2
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Equivalent fault detection code.
Alan Mishchenko
2016-11-09
3
-0
/
+5
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New feature for area minimization in standard cell mapping.
Alan Mishchenko
2016-05-19
1
-0
/
+5
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*
Factoring out library preprocessing code in &nf and putting it elsewhere.
Alan Mishchenko
2016-05-16
3
-0
/
+59
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*
Added switch 'read_genlib -n' to anonymize Genlib library.
Alan Mishchenko
2016-05-16
3
-9
/
+139
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*
Adding API to convert Genlib into a simple Liberty.
Alan Mishchenko
2016-03-11
2
-1
/
+2
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*
Disabling formula cleaner to avoid problems with reading GENLIB on some ↵
Alan Mishchenko
2016-02-21
1
-1
/
+2
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libraries.
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Bug fix in liberty parser and change suggested by Clifford.
Alan Mishchenko
2016-02-07
1
-1
/
+15
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*
GENLIB parsing bug, which led to a crash.
Alan Mishchenko
2016-02-06
1
-1
/
+4
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*
Consolidating timing manager Scl_Con_t and propagating changes.
Alan Mishchenko
2016-01-07
2
-6
/
+5
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*
Migrating to using 32-bit timing representation in &nf.
Alan Mishchenko
2016-01-05
2
-16
/
+16
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*
Migrating back to using 'float' in area-flow computation in &nf.
Alan Mishchenko
2016-01-05
2
-7
/
+9
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*
Corner-case bug in 'read_profile'.
Alan Mishchenko
2015-12-22
1
-1
/
+1
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*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
3
-30
/
+71
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*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-07
4
-1
/
+50
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Adding commands to read/write/print gate profiles.
Alan Mishchenko
2015-12-05
5
-8
/
+250
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*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
4
-1
/
+43
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*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
1
-0
/
+2
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*
Extending and improving timing manager.
Alan Mishchenko
2015-11-08
2
-0
/
+3
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*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-27
2
-0
/
+2
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*
Extending library handling to 8 inputs.
Alan Mishchenko
2015-10-25
2
-1
/
+61
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*
Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only.
Alan Mishchenko
2015-10-23
3
-16
/
+38
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Changes for delay-oriented computation.
Alan Mishchenko
2015-10-23
2
-2
/
+4
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*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-15
2
-0
/
+2
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*
Experiments with precomputation and matching.
Alan Mishchenko
2015-10-12
4
-15
/
+31
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*
Several bug-fixed related to synthesis, library handling, and timimg info.
Alan Mishchenko
2015-09-23
1
-2
/
+4
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*
Updating Mio to use int instead of float.
Alan Mishchenko
2015-08-31
2
-2
/
+192
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*
Important bug fixes in standard-cell library handling and mapper &nf.
Alan Mishchenko
2015-08-28
1
-9
/
+27
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*
Improving the criteria to select representative gates in 'map' with ↵
Alan Mishchenko
2015-04-25
1
-47
/
+60
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floating-point-delay libraries having more than one gate in some functionality classes.
*
Adding platform-independent (alphabetic) way of sorting Genlib gates and ↵
Alan Mishchenko
2015-04-17
2
-20
/
+56
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selecting representatives based on area/delay.
*
Adding APIs to retrieve NOR/OR gates from the library.
Alan Mishchenko
2015-04-14
4
-4
/
+15
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*
Getting default AND-node delay from Genlib library.
Alan Mishchenko
2015-04-06
2
-0
/
+2
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*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
1
-9
/
+9
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*
Major rehash of the CBA code.
Alan Mishchenko
2015-01-31
2
-0
/
+21
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*
Integrating barrier buffers.
Alan Mishchenko
2014-12-08
1
-0
/
+8
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*
Recommended changes for portability.
Alan Mishchenko
2014-10-12
1
-1
/
+1
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*
Suggested patch for type-punned warnings
Alan Mishchenko
2014-10-10
1
-3
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+6
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*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-26
1
-1
/
+1
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*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-26
1
-0
/
+145
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*
Generating abstraction of standard cell library.
Alan Mishchenko
2014-07-25
6
-10
/
+163
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