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yosys-experimental
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src
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map
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scl
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sclDnsize.c
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Author
Age
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*
Cleaning up buffering code.
Alan Mishchenko
2013-10-13
1
-2
/
+0
|
*
Normalization of slew/load values.
Alan Mishchenko
2013-10-13
1
-3
/
+3
|
*
Normalization of slew/load values.
Alan Mishchenko
2013-10-13
1
-2
/
+2
|
*
Integrating input driving cell constraint into buffering/sizing.
Alan Mishchenko
2013-09-17
1
-1
/
+2
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*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-1
/
+1
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-4
/
+9
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-15
/
+1
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-0
/
+6
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-08
1
-10
/
+13
|
*
Adding code to estimate buffer trees.
Alan Mishchenko
2013-08-05
1
-1
/
+1
|
*
Change from input slew to input drive strength in the BLIF file.
Alan Mishchenko
2013-08-04
1
-0
/
+2
|
*
Restructuring gate-sizing code trying to separate timing analysis.
Alan Mishchenko
2013-07-21
1
-2
/
+1
|
*
Improvements to post-mapping re-sizing.
Alan Mishchenko
2013-07-21
1
-27
/
+29
|
*
Improvements to the SCL package.
Alan Mishchenko
2013-07-20
1
-1
/
+2
|
*
Added command 'dnsize' to complement command 'upsize'.
Alan Mishchenko
2013-07-20
1
-0
/
+352