| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Compiler warning. | Alan Mishchenko | 2013-07-29 | 1 | -1/+1 |
| * | Improved buffering. | Alan Mishchenko | 2013-07-29 | 1 | -8/+47 |
| * | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-24 | 1 | -3/+17 |
| * | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-23 | 1 | -1/+2 |
| * | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-23 | 1 | -1/+1 |
| * | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-23 | 1 | -43/+69 |
| * | Generating GENLIB library from SCL. | Alan Mishchenko | 2013-07-22 | 1 | -52/+246 |
| * | Restructuring gate-sizing code trying to separate timing analysis. | Alan Mishchenko | 2013-07-21 | 1 | -0/+904 |
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index : iCE40/abc | |
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