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yosys-experimental
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scl
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sclLib.h
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Author
Age
Files
Lines
*
Unifying standard cell library representations.
Alan Mishchenko
2013-09-17
1
-2
/
+2
*
Infrastructure to support full Liberty format and unitification of library re...
Alan Mishchenko
2013-09-15
1
-8
/
+15
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-11
1
-1
/
+1
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-10
1
-5
/
+5
*
Enable wire load estimation in buffering/sizing.
Alan Mishchenko
2013-08-10
1
-0
/
+1
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-09
1
-8
/
+21
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-2
/
+9
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-17
/
+16
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-08
1
-8
/
+29
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-06
1
-0
/
+2
*
Adding code to estimate buffer trees.
Alan Mishchenko
2013-08-05
1
-0
/
+1
*
Improved buffering.
Alan Mishchenko
2013-07-29
1
-0
/
+1
*
Tuning standard-cell mapping flow.
Alan Mishchenko
2013-07-23
1
-2
/
+3
*
Generating GENLIB library from SCL.
Alan Mishchenko
2013-07-22
1
-1
/
+101
*
Restructuring gate-sizing code trying to separate timing analysis.
Alan Mishchenko
2013-07-21
1
-0
/
+458