iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Memory leak in scl package.	Alan Mishchenko	2016-10-12	1	-0/+2
*	Adding API to convert Genlib into a simple Liberty.	Alan Mishchenko	2016-03-11	1	-0/+1
*	Improvements to timing optimization.	Alan Mishchenko	2015-11-11	1	-4/+4
*	Extending and improving timing manager.	Alan Mishchenko	2015-11-08	1	-12/+27
*	Extending and improving timing manager.	Alan Mishchenko	2015-11-08	1	-0/+134
*	Improvements to Scl_Lib/SC_Cell data-structure.	Alan Mishchenko	2015-09-24	1	-110/+88
*	New switch in 'read_lib' to replace gate/pin names by short strings.	Alan Mishchenko	2015-08-24	1	-0/+1
*	Integrating barrier buffers.	Alan Mishchenko	2014-12-13	1	-0/+1
*	Support for leakage power in Liberty parser and sizer.	Alan Mishchenko	2014-09-16	1	-1/+3
*	Fixing Liberty parser to handle 'scalar' delay/slew tables.	Alan Mishchenko	2014-02-06	1	-0/+9
*	Several changes to allow Liberty files without delay info.	Alan Mishchenko	2013-11-21	1	-0/+3
*	Fixing the wire-load approximation problem.	Alan Mishchenko	2013-11-07	1	-2/+2
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-10-13	1	-0/+1
*	Normalization of slew/load values.	Alan Mishchenko	2013-10-13	1	-5/+0
*	Normalization of slew/load values.	Alan Mishchenko	2013-10-13	1	-0/+1
*	Bug fixes in the library processing,.	Alan Mishchenko	2013-10-02	1	-0/+1
*	Debugging and finetuning the flow.	Alan Mishchenko	2013-09-17	1	-0/+15
*	Unifying standard cell library representations.	Alan Mishchenko	2013-09-17	1	-2/+2
*	Infrastructure to support full Liberty format and unitification of library re...	Alan Mishchenko	2013-09-15	1	-8/+15
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-11	1	-1/+1
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-10	1	-5/+5
*	Enable wire load estimation in buffering/sizing.	Alan Mishchenko	2013-08-10	1	-0/+1
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-09	1	-8/+21
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	1	-2/+9
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	1	-17/+16
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-08	1	-8/+29
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-06	1	-0/+2
*	Adding code to estimate buffer trees.	Alan Mishchenko	2013-08-05	1	-0/+1
*	Improved buffering.	Alan Mishchenko	2013-07-29	1	-0/+1
*	Tuning standard-cell mapping flow.	Alan Mishchenko	2013-07-23	1	-2/+3
*	Generating GENLIB library from SCL.	Alan Mishchenko	2013-07-22	1	-1/+101
*	Restructuring gate-sizing code trying to separate timing analysis.	Alan Mishchenko	2013-07-21	1	-0/+458