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path: root/src/map/scl/sclLib.h
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* Several changes to allow Liberty files without delay info.Alan Mishchenko2013-11-211-0/+3
* Fixing the wire-load approximation problem.Alan Mishchenko2013-11-071-2/+2
* Improvements to buffering and sizing.Alan Mishchenko2013-10-131-0/+1
* Normalization of slew/load values.Alan Mishchenko2013-10-131-5/+0
* Normalization of slew/load values.Alan Mishchenko2013-10-131-0/+1
* Bug fixes in the library processing,.Alan Mishchenko2013-10-021-0/+1
* Debugging and finetuning the flow.Alan Mishchenko2013-09-171-0/+15
* Unifying standard cell library representations.Alan Mishchenko2013-09-171-2/+2
* Infrastructure to support full Liberty format and unitification of library re...Alan Mishchenko2013-09-151-8/+15
* Integrated buffering and sizing.Alan Mishchenko2013-08-111-1/+1
* Integrated buffering and sizing.Alan Mishchenko2013-08-101-5/+5
* Enable wire load estimation in buffering/sizing.Alan Mishchenko2013-08-101-0/+1
* Integrated buffering and sizing.Alan Mishchenko2013-08-091-8/+21
* Improvements to buffering and sizing.Alan Mishchenko2013-08-091-2/+9
* Improvements to buffering and sizing.Alan Mishchenko2013-08-091-17/+16
* Integrated buffering and sizing.Alan Mishchenko2013-08-081-8/+29
* Improvements to buffering and sizing.Alan Mishchenko2013-08-061-0/+2
* Adding code to estimate buffer trees.Alan Mishchenko2013-08-051-0/+1
* Improved buffering.Alan Mishchenko2013-07-291-0/+1
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-231-2/+3
* Generating GENLIB library from SCL.Alan Mishchenko2013-07-221-1/+101
* Restructuring gate-sizing code trying to separate timing analysis.Alan Mishchenko2013-07-211-0/+458