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yosys-experimental
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scl
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sclLoad.c
Commit message (
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Author
Age
Files
Lines
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-15
/
+15
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-2
/
+2
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-08
1
-3
/
+3
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-06
1
-1
/
+18
*
Adding code to estimate buffer trees.
Alan Mishchenko
2013-08-05
1
-0
/
+20
*
Change from input slew to input drive strength in the BLIF file.
Alan Mishchenko
2013-08-04
1
-9
/
+27
*
Restructuring gate-sizing code trying to separate timing analysis.
Alan Mishchenko
2013-07-21
1
-59
/
+1
*
Adding support for input slew and output capacitance to timer and gate-sizer.
Alan Mishchenko
2013-07-21
1
-1
/
+10
*
Improvements to gate sizing.
Alan Mishchenko
2012-10-08
1
-34
/
+60
*
Improving print-outs in 'stime' and 'gsize'.
Alan Mishchenko
2012-09-04
1
-1
/
+3
*
Several minor changes.
Alan Mishchenko
2012-09-03
1
-1
/
+1
*
New package to read/write a subset of Liberty for STA.
Alan Mishchenko
2012-09-01
1
-2
/
+2
*
Handling constant nodes in gate sizing.
Alan Mishchenko
2012-08-30
1
-2
/
+2
*
New package to read/write a subset of Liberty for STA.
Alan Mishchenko
2012-08-29
1
-0
/
+180