iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Improvements to Scl_Lib/SC_Cell data-structure.	Alan Mishchenko	2015-09-24	1	-3/+3
*	Corner case bug in wire-cap estimation.	Alan Mishchenko	2015-02-18	1	-0/+2
*	Integrating barrier buffers.	Alan Mishchenko	2014-12-13	1	-0/+9
*	Fixing the wire-load approximation problem.	Alan Mishchenko	2013-11-07	1	-13/+25
*	Debugging and finetuning the flow.	Alan Mishchenko	2013-09-17	1	-1/+1
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-10	1	-4/+5
*	Enable wire load estimation in buffering/sizing.	Alan Mishchenko	2013-08-10	1	-6/+6
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	1	-15/+15
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-09	1	-2/+2
*	Integrated buffering and sizing.	Alan Mishchenko	2013-08-08	1	-3/+3
*	Improvements to buffering and sizing.	Alan Mishchenko	2013-08-06	1	-1/+18
*	Adding code to estimate buffer trees.	Alan Mishchenko	2013-08-05	1	-0/+20
*	Change from input slew to input drive strength in the BLIF file.	Alan Mishchenko	2013-08-04	1	-9/+27
*	Restructuring gate-sizing code trying to separate timing analysis.	Alan Mishchenko	2013-07-21	1	-59/+1
*	Adding support for input slew and output capacitance to timer and gate-sizer.	Alan Mishchenko	2013-07-21	1	-1/+10
*	Improvements to gate sizing.	Alan Mishchenko	2012-10-08	1	-34/+60
*	Improving print-outs in 'stime' and 'gsize'.	Alan Mishchenko	2012-09-04	1	-1/+3
*	Several minor changes.	Alan Mishchenko	2012-09-03	1	-1/+1
*	New package to read/write a subset of Liberty for STA.	Alan Mishchenko	2012-09-01	1	-2/+2
*	Handling constant nodes in gate sizing.	Alan Mishchenko	2012-08-30	1	-2/+2
*	New package to read/write a subset of Liberty for STA.	Alan Mishchenko	2012-08-29	1	-0/+180