index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
map
/
scl
/
sclSize.h
Commit message (
Collapse
)
Author
Age
Files
Lines
*
Improvements and tuning of CBA with buffering/sizing.
Alan Mishchenko
2015-02-04
1
-3
/
+3
|
*
Gate sizing with barrier buffers.
Alan Mishchenko
2014-12-21
1
-0
/
+1
|
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-13
1
-1
/
+4
|
*
Bug fix in timing update.
Alan Mishchenko
2013-11-26
1
-1
/
+1
|
*
Improvements to the standard cell flow.
Alan Mishchenko
2013-11-08
1
-1
/
+1
|
*
Organizing the timing report functions.
Alan Mishchenko
2013-11-07
1
-7
/
+6
|
*
Fixing the wire-load approximation problem.
Alan Mishchenko
2013-11-07
1
-1
/
+1
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-10-13
1
-3
/
+3
|
*
Cleaning up buffering code.
Alan Mishchenko
2013-10-13
1
-1
/
+0
|
*
Normalization of slew/load values.
Alan Mishchenko
2013-10-13
1
-4
/
+6
|
*
Changing default values.
Alan Mishchenko
2013-10-02
1
-2
/
+2
|
*
Integrating input driving cell constraint into buffering/sizing.
Alan Mishchenko
2013-09-17
1
-0
/
+2
|
*
Debugging and finetuning the flow.
Alan Mishchenko
2013-09-17
1
-0
/
+21
|
*
Adding commands to set and print timing constraints.
Alan Mishchenko
2013-09-17
1
-0
/
+1
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-11
1
-1
/
+11
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-11
1
-1
/
+10
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-10
1
-1
/
+1
|
*
Enable wire load estimation in buffering/sizing.
Alan Mishchenko
2013-08-10
1
-2
/
+4
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-09
1
-1
/
+1
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-09
1
-1
/
+1
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-09
1
-1
/
+9
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-1
/
+8
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-15
/
+29
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-38
/
+22
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-09
1
-56
/
+101
|
*
Integrated buffering and sizing.
Alan Mishchenko
2013-08-08
1
-9
/
+17
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-07
1
-14
/
+30
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-06
1
-0
/
+30
|
*
Improvements to buffering and sizing.
Alan Mishchenko
2013-08-06
1
-1
/
+2
|
*
Adding new (un)buffering with phase information.
Alan Mishchenko
2013-08-05
1
-0
/
+2
|
*
Adding code to estimate buffer trees.
Alan Mishchenko
2013-08-05
1
-2
/
+7
|
*
Change from input slew to input drive strength in the BLIF file.
Alan Mishchenko
2013-08-04
1
-1
/
+4
|
*
Adding switch 'buffer -p' to enable buffing of the primary inputs.
Alan Mishchenko
2013-08-02
1
-1
/
+1
|
*
Added commands 'maxsize' and 'unbuffer'.
Alan Mishchenko
2013-07-29
1
-0
/
+1
|
*
Improved buffering.
Alan Mishchenko
2013-07-29
1
-11
/
+23
|
*
Improved gate-sizing.
Alan Mishchenko
2013-07-29
1
-0
/
+2
|
*
Tuning standard-cell mapping flow.
Alan Mishchenko
2013-07-24
1
-2
/
+3
|
*
Tuning standard-cell mapping flow.
Alan Mishchenko
2013-07-23
1
-3
/
+3
|
*
Generating GENLIB library from SCL.
Alan Mishchenko
2013-07-22
1
-0
/
+1
|
*
Restructuring gate-sizing code trying to separate timing analysis.
Alan Mishchenko
2013-07-21
1
-0
/
+405