Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Adding new (un)buffering with phase information. | Alan Mishchenko | 2013-08-05 | 1 | -0/+2 |
* | Adding code to estimate buffer trees. | Alan Mishchenko | 2013-08-05 | 1 | -2/+7 |
* | Change from input slew to input drive strength in the BLIF file. | Alan Mishchenko | 2013-08-04 | 1 | -1/+4 |
* | Adding switch 'buffer -p' to enable buffing of the primary inputs. | Alan Mishchenko | 2013-08-02 | 1 | -1/+1 |
* | Added commands 'maxsize' and 'unbuffer'. | Alan Mishchenko | 2013-07-29 | 1 | -0/+1 |
* | Improved buffering. | Alan Mishchenko | 2013-07-29 | 1 | -11/+23 |
* | Improved gate-sizing. | Alan Mishchenko | 2013-07-29 | 1 | -0/+2 |
* | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-24 | 1 | -2/+3 |
* | Tuning standard-cell mapping flow. | Alan Mishchenko | 2013-07-23 | 1 | -3/+3 |
* | Generating GENLIB library from SCL. | Alan Mishchenko | 2013-07-22 | 1 | -0/+1 |
* | Restructuring gate-sizing code trying to separate timing analysis. | Alan Mishchenko | 2013-07-21 | 1 | -0/+405 |