Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Experiments with the mapper. | Alan Mishchenko | 2022-06-23 | 5 | -0/+73 |
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* | Adding switch to dsd_match to skip small functions. | Alan Mishchenko | 2022-05-18 | 2 | -5/+5 |
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* | Merge pull request #145 from QuantamHD/fix_internal_pins | alanminko | 2022-04-04 | 1 | -1/+5 |
|\ | | | | | Fixes internal pin parsing error in ASAP7 liberty file. | ||||
| * | Fixes internal pin parsing error in ASAP7 liberty file. | QuantamHD | 2021-12-20 | 1 | -1/+5 |
| | | | | | | | | | | | | | | This fix addresses an issue I saw with the ASAP7 liberty files and ABC. ASAP7 lists internal pins in its liberty file which ABC's liberty parser doesn't account for. This causes an assert to be triggered. This fix simply adds interal pins to the ignore list. | ||||
* | | Suggested changes for the case when the file begings with a new line. | Alan Mishchenko | 2022-03-29 | 2 | -53/+74 |
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* | | Suggested bug fixes in the old code. | Alan Mishchenko | 2022-01-21 | 1 | -4/+3 |
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* | Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers. | Alan Mishchenko | 2021-09-26 | 2 | -2/+2 |
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* | Two rare corner-case bugs in &if mapper. | Alan Mishchenko | 2021-09-26 | 1 | -1/+1 |
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* | Experiments with CEC. | Alan Mishchenko | 2021-07-10 | 1 | -2/+2 |
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* | Experiments with MUX decomposition. | Alan Mishchenko | 2021-07-08 | 1 | -4/+4 |
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* | Updating LUT synthesis code. | Alan Mishchenko | 2021-05-26 | 1 | -0/+1 |
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* | Several changes for standard mapping. | Alan Mishchenko | 2021-04-28 | 1 | -2/+13 |
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* | Updating the mapper when user-specific matching is used. | Alan Mishchenko | 2021-01-09 | 1 | -0/+12 |
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* | Rare bug fix in mapping with choices. | Alan Mishchenko | 2020-10-29 | 1 | -1/+2 |
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* | Compiler warnings. | Alan Mishchenko | 2020-05-03 | 1 | -1/+0 |
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* | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 2 | -30/+30 |
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* | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 1 | -1/+1 |
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* | Adding dumping of genlib library in Verilog. | Alan Mishchenko | 2020-05-03 | 4 | -7/+110 |
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* | Adding dynamic memory alloc for the buffer in Liberty file reader. | Alan Mishchenko | 2020-01-11 | 1 | -3/+9 |
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* | Making sure arrival time of constant node is -infinity. | Alan Mishchenko | 2020-01-02 | 1 | -0/+2 |
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* | Adding limit on the depth of recursion when counting exact area in 'amap'. | Alan Mishchenko | 2019-10-26 | 3 | -1/+62 |
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* | Small bug in the unused code. | Alan Mishchenko | 2019-10-04 | 1 | -1/+1 |
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* | Adding switch to &if to consider special type of 6-input cuts. | Alan Mishchenko | 2019-09-26 | 4 | -0/+84 |
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* | Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to ↵ | Alan Mishchenko | 2019-09-19 | 1 | -0/+1 |
| | | | | print delay profile. | ||||
* | Fixing some update gcc. | Alan Mishchenko | 2019-07-24 | 1 | -1/+1 |
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* | Adding support for user-specified wire delays in &if. | Alan Mishchenko | 2019-05-29 | 1 | -1/+1 |
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* | Prevent assertions from firing for deep logic networks. | Alan Mishchenko | 2019-03-20 | 1 | -4/+4 |
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* | Fixing some warnings by adding cast from 'int' to 'size_t' in memset, ↵ | Alan Mishchenko | 2019-03-05 | 17 | -26/+26 |
| | | | | memcpy, etc. | ||||
* | Fixing some warnings with -Wconversion. | Alan Mishchenko | 2019-03-05 | 1 | -2/+2 |
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* | Fixing float overflow during edge-flow computation in 'if' mapper (change to ↵ | Alan Mishchenko | 2018-12-12 | 1 | -0/+8 |
| | | | | avoid dependence on the order of additions). | ||||
* | Fixing float overflow during edge-flow computation in 'if' mapper. | Alan Mishchenko | 2018-12-12 | 1 | -3/+7 |
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* | Adding switch &w -n to modify the comment section of the AIGER file written. | Alan Mishchenko | 2018-11-21 | 1 | -2/+2 |
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* | Skip cells in Liberty files which have dont_use attribute. | Alan Mishchenko | 2018-10-18 | 2 | -3/+56 |
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* | Suggested bug fix in 'amap'. | Alan Mishchenko | 2018-09-13 | 1 | -0/+3 |
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* | Adding parameters and improvements to %blast. | Alan Mishchenko | 2018-02-28 | 2 | -0/+8 |
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* | Compilation problem with pow(). | Alan Mishchenko | 2018-02-19 | 1 | -2/+2 |
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* | Value of properties can be expression. | Staf Verhaegen | 2018-01-03 | 1 | -0/+12 |
| | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done. | ||||
* | Adding API to dump MiniAIG into a Verilog file and other small changes. | Alan Mishchenko | 2017-10-22 | 2 | -0/+3 |
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* | Fix typo on the message reporting max output load. | Alan Mishchenko | 2017-10-11 | 1 | -1/+1 |
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* | Updates and bug fixes. | Alan Mishchenko | 2017-10-04 | 3 | -11/+19 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-24 | 5 | -3/+57 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-20 | 2 | -3/+7 |
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* | Maintenance and updates. | Alan Mishchenko | 2017-09-18 | 4 | -0/+56 |
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* | Compiler warnings. | Alan Mishchenko | 2017-07-22 | 6 | -8/+8 |
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* | Synchronizing various data-structures. | Alan Mishchenko | 2017-07-04 | 2 | -7/+162 |
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* | Saturating floating point computation. | Alan Mishchenko | 2017-07-01 | 1 | -3/+7 |
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* | Saturating floating point computation. | Alan Mishchenko | 2017-06-29 | 1 | -4/+10 |
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* | Experiments with new network data-structure. | Alan Mishchenko | 2017-03-20 | 2 | -0/+2 |
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* | Experiments with new network data-structure. | Alan Mishchenko | 2017-03-19 | 1 | -1/+1 |
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* | stringizing macro argument | Heinz Riener | 2017-03-03 | 1 | -2/+2 |
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