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* Improving the criteria to select representative gates in 'map' with ↵Alan Mishchenko2015-04-251-47/+60
| | | | floating-point-delay libraries having more than one gate in some functionality classes.
* Adding switch 'map -f' to not use large gates for high-fanout nodes ↵Alan Mishchenko2015-04-244-2/+5
| | | | (disabled by default).
* Adding platform-independent (alphabetic) way of sorting Genlib gates and ↵Alan Mishchenko2015-04-172-20/+56
| | | | selecting representatives based on area/delay.
* Adding APIs to retrieve NOR/OR gates from the library.Alan Mishchenko2015-04-144-4/+15
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* Getting default AND-node delay from Genlib library.Alan Mishchenko2015-04-062-0/+2
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* Support for representing programmable cell configuration data (bug fix).Alan Mishchenko2015-03-091-1/+4
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* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-081-1/+2
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* Support for representing programmable cell configuration data.Alan Mishchenko2015-03-083-64/+222
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* Experiments with SAT-based cube enumeration.Alan Mishchenko2015-03-051-3/+4
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* Corner case bug in wire-cap estimation.Alan Mishchenko2015-02-181-0/+2
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* Several improvements to CBA data-structure.Alan Mishchenko2015-02-091-1/+1
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* Fixed a typo in variable names.Alan Mishchenko2015-02-075-24/+24
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* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-045-28/+77
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* Improvements and tuning of CBA.Alan Mishchenko2015-02-011-0/+2
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* Major rehash of the CBA code.Alan Mishchenko2015-01-312-0/+21
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* New assertions and bug fix in DSD balancing.Alan Mishchenko2015-01-272-8/+11
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* Gate sizing with barrier buffers.Alan Mishchenko2014-12-213-1/+52
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* Exprimental features in tech-mapping.Alan Mishchenko2014-12-211-2/+3
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* Bug fix in reading box library.Alan Mishchenko2014-12-201-1/+1
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* Integrating barrier buffers.Alan Mishchenko2014-12-135-10/+76
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* Adding new mapping feature.Alan Mishchenko2014-12-114-18/+56
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* Integrating barrier buffers.Alan Mishchenko2014-12-081-0/+8
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* Bug fix in truth table computation.Alan Mishchenko2014-10-151-11/+9
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* Recommended changes for portability.Alan Mishchenko2014-10-121-1/+1
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* MUX decomposition during mapping.Alan Mishchenko2014-10-111-1/+0
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* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-1/+2
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* Suggested patch for type-punned warningsAlan Mishchenko2014-10-101-3/+6
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* Small changes.Alan Mishchenko2014-10-081-0/+2
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* Compiler warnings.Alan Mishchenko2014-10-082-1/+3
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* Detection of threshold functions.Alan Mishchenko2014-10-082-0/+74
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* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-2/+9
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* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-043-15/+126
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* Deriving AIG after cell mapping.Alan Mishchenko2014-10-032-0/+11
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* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
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* Synchronizing packages.Alan Mishchenko2014-09-202-3/+3
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* Synchronizing packages.Alan Mishchenko2014-09-201-0/+2
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* Updating command 'dsd_clean'.Alan Mishchenko2014-09-203-3/+16
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* Updating DSD balance to handle XOR gate as having the same delay as AND gate.Alan Mishchenko2014-09-194-10/+11
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* Improvements to Boolean matching.Alan Mishchenko2014-09-192-33/+98
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* Improvements to Boolean matching.Alan Mishchenko2014-09-196-66/+474
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* Improvements to Boolean matching.Alan Mishchenko2014-09-182-6/+22
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* Improvements to Boolean matching.Alan Mishchenko2014-09-184-5/+29
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* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+29
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* Improving DSD manager.Alan Mishchenko2014-09-182-0/+69
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* Concurrency for Boolean matching.Alan Mishchenko2014-09-184-47/+263
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* Improvements to Boolean matching.Alan Mishchenko2014-09-173-60/+191
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* Support for leakage power in Liberty parser and sizer.Alan Mishchenko2014-09-165-5/+122
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* New choice computation.Alan Mishchenko2014-09-161-9/+9
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* Improvements to Boolean matching.Alan Mishchenko2014-09-161-201/+554
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* Improvements to the timing manager.Alan Mishchenko2014-08-251-2/+2
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