index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
misc
Commit message (
Collapse
)
Author
Age
Files
Lines
...
*
Changes to the ABC data-structures to allow for larger designs.
Alan Mishchenko
2013-05-04
1
-2
/
+2
|
*
Compiler warnings.
Alan Mishchenko
2013-05-03
1
-1
/
+0
|
*
Reading/writing MiniAIG and several minor changes.
Alan Mishchenko
2013-05-03
1
-0
/
+19
|
*
Minor changes and improvement in PO partitioning (command &popart).
Alan Mishchenko
2013-05-01
1
-0
/
+14
|
*
Faster isomorphism detection (command &iso).
Alan Mishchenko
2013-05-01
1
-1
/
+92
|
*
SAT sweeping under constraints.
Alan Mishchenko
2013-04-28
1
-0
/
+20
|
*
New fast extract.
Alan Mishchenko
2013-04-27
5
-1
/
+860
|
*
Shrink for 6-LUTs.
Alan Mishchenko
2013-03-31
1
-2
/
+138
|
*
Adding command &miter2 to derive a specified sequential miter.
Alan Mishchenko
2013-03-27
2
-0
/
+27
|
*
PO partitioning algorithm.
Alan Mishchenko
2013-03-09
1
-12
/
+10
|
*
Integrating box library.
Alan Mishchenko
2013-03-08
1
-0
/
+1
|
*
Improvements to the hierarchy/timing manager.
Alan Mishchenko
2013-03-05
2
-0
/
+10
|
*
Improvements to the hierarchy/timing manager.
Alan Mishchenko
2013-03-05
4
-20
/
+78
|
*
User-controlable SAT sweeper and other small changes.
Alan Mishchenko
2013-02-27
2
-4
/
+2
|
*
User-controlable SAT sweeper.
Alan Mishchenko
2013-02-26
1
-0
/
+8
|
*
User-controlable SAT sweeper.
Alan Mishchenko
2013-02-25
1
-1
/
+2
|
*
User-controlable SAT sweeper.
Alan Mishchenko
2013-02-25
1
-0
/
+5
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-23
1
-1
/
+3
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-23
2
-3
/
+5
|
*
Allowing for Verilog names of the type slash-<name>-space-[N].
Alan Mishchenko
2013-02-22
1
-2
/
+8
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-0
/
+1
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-7
/
+8
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-20
1
-1
/
+1
|
*
Integrating hierarchy information (reporting incorrect topological order).
Alan Mishchenko
2013-02-20
2
-0
/
+24
|
*
Adding STG generation (&era -d) and STG encoding (&read_stg <file>).
Alan Mishchenko
2013-02-19
1
-0
/
+1
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-19
1
-27
/
+35
|
*
Integrating sweeping information.
Alan Mishchenko
2013-02-18
2
-6
/
+136
|
*
Integration of timing manager.
Alan Mishchenko
2013-02-03
1
-1
/
+1
|
*
Integration of timing manager.
Alan Mishchenko
2013-02-01
1
-0
/
+1
|
*
Integration of timing manager.
Alan Mishchenko
2013-01-30
1
-0
/
+2
|
*
Fixing compilation problems on Linux-32 related to constants of type ↵
Alan Mishchenko
2013-01-30
3
-80
/
+86
|
|
|
|
unsigned long long.
*
Updated CEX code to handle trivial CEX of the type (Abc_Cex_t*)1.
Alan Mishchenko
2013-01-25
1
-0
/
+19
|
*
Integration of timing manager.
Alan Mishchenko
2013-01-25
1
-3
/
+10
|
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-1
/
+2
|
*
Integration of timing manager.
Alan Mishchenko
2013-01-23
1
-2
/
+4
|
*
Fixing C++ compilation issues.
Alan Mishchenko
2013-01-08
2
-4
/
+8
|
*
Technology mapper.
Alan Mishchenko
2013-01-08
1
-0
/
+253
|
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-15
2
-5
/
+51
|
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-13
2
-10
/
+22
|
*
Assembling timing/hierarchy manager from input data.
Alan Mishchenko
2012-12-10
2
-0
/
+62
|
*
Unifification of custom extensions.
Alan Mishchenko
2012-12-10
3
-32
/
+31
|
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-3
/
+4
|
*
Deriving CEX after phase/tempor/reparam.
Alan Mishchenko
2012-12-09
1
-6
/
+5
|
*
Deriving CEX after phase/tempor/reparam.
Alan Mishchenko
2012-12-08
2
-1
/
+118
|
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-30
1
-2
/
+2
|
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-29
2
-0
/
+20
|
*
Counter-example analysis and optimization.
Alan Mishchenko
2012-11-28
2
-0
/
+12
|
*
DSD manager.
Alan Mishchenko
2012-11-20
1
-5
/
+5
|
*
DSD manager.
Alan Mishchenko
2012-11-19
1
-0
/
+1
|
*
Added switch 'cexcut -m' to generate bad states for all frames after G.
Alan Mishchenko
2012-11-15
1
-2
/
+2
|
[prev]
[next]