index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
proof
/
cec
/
cecSolve.c
Commit message (
Collapse
)
Author
Age
Files
Lines
*
Corner case bug fix in &sat -a.
Alan Mishchenko
2020-03-18
1
-3
/
+12
|
*
Adding switch &w -n to modify the comment section of the AIGER file written.
Alan Mishchenko
2018-11-21
1
-1
/
+1
|
*
Bug fix in &sat -x.
Alan Mishchenko
2018-05-07
1
-0
/
+2
|
*
Adding &sat -x to save CEXes for multi-output combinational miters.
Alan Mishchenko
2018-05-06
1
-0
/
+20
|
*
Adding new command 'dump_equiv'.
Alan Mishchenko
2016-07-21
1
-1
/
+11
|
*
Enabling circuit solver in &fraig.
Alan Mishchenko
2014-08-12
1
-0
/
+69
|
*
Adding a wrapper around clock() for more accurate time counting in ABC.
Alan Mishchenko
2013-05-27
1
-31
/
+31
|
*
Unifification of custom extensions.
Alan Mishchenko
2012-12-10
1
-1
/
+1
|
*
Bug fix: no need to normalize const0 node.
Alan Mishchenko
2012-09-17
1
-2
/
+2
|
*
Fixing time primtouts throughout the code.
Alan Mishchenko
2012-07-07
1
-6
/
+11
|
*
Bug fix for incorrect memory allocation in main SAT solver, leading to ↵
Alan Mishchenko
2012-01-23
1
-1
/
+1
|
|
|
|
crashes in 'dsec' (correction to the previous fix).
*
Bug fix for incorrect memory allocation in main SAT solver, leading to ↵
Alan Mishchenko
2012-01-22
1
-1
/
+1
|
|
|
|
crashes in 'dsec'.
*
Major restructuring of the code.
Alan Mishchenko
2012-01-21
1
-0
/
+1023