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* Experimental simulation.Alan Mishchenko2020-06-032-1/+100
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* Dumping BDD variable order after 'clp'.Alan Mishchenko2020-05-186-10/+27
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* Experimental resubstitution.Alan Mishchenko2020-05-157-263/+512
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* Experimental resubstitution.Alan Mishchenko2020-05-131-67/+221
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* Experimental resubstitution.Alan Mishchenko2020-05-111-4/+10
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* Adding new utility procedures.Alan Mishchenko2020-05-116-45/+159
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* Adding new utility procedures.Alan Mishchenko2020-05-103-9/+172
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* Experimental resubstitution.Alan Mishchenko2020-05-082-37/+125
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* Experimental resubstitution.Alan Mishchenko2020-05-071-35/+87
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* Experimental resubstitution.Alan Mishchenko2020-05-072-233/+450
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* Fixing the accidentally broken build.Alan Mishchenko2020-05-061-1/+0
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* Experiment with permutations.Alan Mishchenko2020-05-031-1/+1
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* Experiment with permutations.Alan Mishchenko2020-05-032-1/+97
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* Compiler warnings and errors.Alan Mishchenko2020-05-034-8/+8
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* Compiler warnings.Alan Mishchenko2020-05-032-2/+0
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* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-032-30/+30
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* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-031-1/+1
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* Adding dumping of genlib library in Verilog.Alan Mishchenko2020-05-034-7/+110
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* Experimental resubstitution.Alan Mishchenko2020-05-039-5/+1049
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* Merge pull request #57 from whitequark/patch-1alanminko2020-04-301-2/+2
|\ | | | | Make use of setrlimit conditional on ABC_NO_RLIMIT
| * Make use of setrlimit conditional on ABC_NO_RLIMIT.whitequark2020-04-301-2/+2
| | | | | | | | | | This is useful for POSIX-like platforms that do not have rlimit, such as WASI.
| * Gia_ManDupPermFlop to behave as Gia_ManDupPermEddie Hung2020-04-271-5/+7
| | | | | | | | Fixes sequential synthesis (e.g. &scl) for multiple domains
* | Merge pull request #65 from FPGeh/fix_seq_synthalanminko2020-04-301-5/+7
|\ \ | | | | | | Gia_ManDupPermFlop to behave as Gia_ManDupPerm
| * | Gia_ManDupPermFlop to behave as Gia_ManDupPermEddie Hung2020-01-231-5/+7
| | | | | | | | | | | | Fixes sequential synthesis (e.g. &scl) for multiple domains
* | | Adding new API to MiniAIG.Alan Mishchenko2020-04-291-2/+2
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* | | Adding new API to MiniAIG.Alan Mishchenko2020-04-292-0/+210
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* | | Bug fix in 'resub' to enable additional divisors, by Siang-Yun Lee.Alan Mishchenko2020-04-271-124/+368
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* | New AIG restructuring feature.Alan Mishchenko2020-04-232-0/+230
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* | Fix a bug in comb loop detection.Alan Mishchenko2020-04-224-17/+22
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* | Improving simulation patterns by local search.Alan Mishchenko2020-04-171-0/+1
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* | Improving simulation patterns by local search.Alan Mishchenko2020-04-173-38/+528
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* | Fixing broken build and compiler warnings.Alan Mishchenko2020-04-175-7/+7
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* | Fixing broken build and compiler warnings.Alan Mishchenko2020-04-171-1/+1
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* | Fixing broken build and compiler warnings.Alan Mishchenko2020-04-1710-12/+12
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* | Removing debug stop.Alan Mishchenko2020-04-171-4/+0
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* | Memory leak.Alan Mishchenko2020-04-171-0/+3
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* | Adding check for comb loops in NDR.Alan Mishchenko2020-04-173-1/+141
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* | QBF-based code generation (extending beyond 32 bits).Alan Mishchenko2020-04-131-25/+44
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* | QBF-based code generation.Alan Mishchenko2020-04-121-9/+9
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* | QBF-based code generation.Alan Mishchenko2020-04-122-6/+275
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* | Procedures to explore structural support of an AIG.Alan Mishchenko2020-04-102-0/+96
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* | Various changes.Alan Mishchenko2020-04-102-1/+3
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* | Various changes.Alan Mishchenko2020-04-103-20/+151
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* | Debugging a combo loop in NDR.Alan Mishchenko2020-04-091-2/+3
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* | Adding option to &saveaig to compare AIGs by node count.Alan Mishchenko2020-04-091-0/+3
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* | Various changes.Alan Mishchenko2020-04-083-41/+86
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* | Adding option to &saveaig to compare AIGs by node count.Alan Mishchenko2020-04-071-1/+1
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* | Adding option to &saveaig to compare AIGs by node count.Alan Mishchenko2020-04-071-1/+4
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* | Corner-case bug fix in SAT-based sim info generation.Alan Mishchenko2020-04-071-4/+6
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* | Correctly updating the failed output when recording the CEX in bmc3 -a.Alan Mishchenko2020-04-031-1/+5
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