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yosys-experimental
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Age
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...
*
Improving bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
2
-16
/
+46
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
4
-1
/
+651
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-12
5
-2
/
+97
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-02-08
3
-95
/
+176
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-02-07
4
-0
/
+654
*
Bug fix in liberty parser and change suggested by Clifford.
Alan Mishchenko
2016-02-07
2
-1
/
+17
*
Added recursive bit-blasting of a carry-lookahead adder.
Alan Mishchenko
2016-02-06
1
-0
/
+51
*
GENLIB parsing bug, which led to a crash.
Alan Mishchenko
2016-02-06
1
-1
/
+4
*
Fixing the problem of identically named signals in 'retime'.
Alan Mishchenko
2016-02-05
2
-4
/
+4
*
Making flop names after 'retime' more meaningful.
Alan Mishchenko
2016-02-03
2
-4
/
+6
*
Preserving internal signal names when 'strash' is not used.
Alan Mishchenko
2016-02-03
2
-0
/
+7
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-1
/
+1
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-6
/
+13
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
4
-11
/
+26
*
An add-on to write Verilog for circuits mapped into simple gates.
Alan Mishchenko
2016-02-01
1
-9
/
+22
*
Rare bug fix in 'dch' resulting in choice nodes having internal fanout.
Alan Mishchenko
2016-01-31
1
-1
/
+8
*
Fixing mismatch in the TLS flow induced by adding cell configs in the DSD man...
Alan Mishchenko
2016-01-30
1
-1
/
+1
*
Small changes to sort for timing.
Alan Mishchenko
2016-01-24
1
-3
/
+7
*
Bug fix in 'aig', for the case of non-min-base SOPs.
Alan Mishchenko
2016-01-20
1
-0
/
+1
*
Generating sorting network as a PLA file.
Alan Mishchenko
2016-01-20
2
-3
/
+52
*
New command to dump LUT network.
Alan Mishchenko
2016-01-16
4
-33
/
+232
*
Compiler warning.
Alan Mishchenko
2016-01-14
1
-1
/
+0
*
Changes to PDR to compute f-inf clauses and import invariant (or clauses) as ...
Alan Mishchenko
2016-01-14
15
-68
/
+457
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-01-14
1
-50
/
+83
*
Adding a way to derive cardinality constraint as a sorting network.
Alan Mishchenko
2016-01-13
1
-4
/
+89
*
Adding support for delay/area tradeoff.
Alan Mishchenko
2016-01-13
5
-36
/
+70
*
Integrating new CNF generation into &bmc.
Alan Mishchenko
2016-01-12
3
-16
/
+26
*
Better print-out of SOPs. Changing default of 'fx'. Updating 'satclp' to fine...
Alan Mishchenko
2016-01-12
5
-10
/
+184
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-01-10
1
-0
/
+1
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-01-10
2
-0
/
+164
*
Adding support of candinality clause to the SAT solver.
Alan Mishchenko
2016-01-10
5
-7
/
+52
*
Consolidating timing manager Scl_Con_t and propagating changes.
Alan Mishchenko
2016-01-07
11
-54
/
+93
*
Bug fix in constraint file reader.
Alan Mishchenko
2016-01-07
2
-2
/
+8
*
Adding switch &miter -x for XORs outputs of two word-level POs.
Alan Mishchenko
2016-01-06
3
-2
/
+57
*
Fixing last-minute bug fix in &nf.
Alan Mishchenko
2016-01-05
1
-2
/
+2
*
Buf fix in floating time reporting.
Alan Mishchenko
2016-01-05
1
-20
/
+21
*
Fix in &nf for the case when PO can be driven by an inverter.
Alan Mishchenko
2016-01-05
1
-0
/
+5
*
Fix in &nf for the case when PO can be driven by an inverter.
Alan Mishchenko
2016-01-05
1
-0
/
+30
*
Migrating to using 32-bit timing representation in &nf.
Alan Mishchenko
2016-01-05
5
-242
/
+239
*
Migrating back to using 'float' in area-flow computation in &nf.
Alan Mishchenko
2016-01-05
5
-77
/
+86
*
Corner-case bug in 'read_profile'.
Alan Mishchenko
2015-12-22
1
-1
/
+1
*
Adding names to GIA inputs/outputs (addressing x-valued flops).
Alan Mishchenko
2015-12-22
1
-1
/
+51
*
Adding names to GIA inputs/outputs. Changing polarity of invariant generated...
Alan Mishchenko
2015-12-22
1
-1
/
+1
*
Adding names to GIA inputs/outputs. Changing polarity of invariant generated...
Alan Mishchenko
2015-12-21
1
-0
/
+34
*
Adding names to GIA inputs/outputs. Changing polarity of invariant generated...
Alan Mishchenko
2015-12-21
1
-1
/
+1
*
Corner-case bug in invariant profiling.
Alan Mishchenko
2015-12-18
1
-0
/
+5
*
Compiler warning.
Alan Mishchenko
2015-12-16
1
-7
/
+0
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
13
-71
/
+252
*
Extending Verilog parser to handle 'default' in the case-statement.
Alan Mishchenko
2015-12-07
1
-11
/
+27
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-07
6
-2
/
+62
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