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iCE40/abc
yosys-experimental
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Age
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*
Major rehash of the CBA code.
Alan Mishchenko
2015-01-31
22
-2779
/
+3448
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-17
/
+17
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-3
/
+1
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-19
/
+93
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-22
/
+93
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
1
-45
/
+61
|
*
Preprocessing for multi-output PLA tables.
Alan Mishchenko
2015-01-31
3
-0
/
+143
|
*
Fixing reported memory alignment issue.
Alan Mishchenko
2015-01-27
1
-0
/
+12
|
*
New assertions and bug fix in DSD balancing.
Alan Mishchenko
2015-01-27
9
-16
/
+90
|
*
Several ongoing changes.
Alan Mishchenko
2015-01-26
1
-1
/
+1
|
*
Several ongoing changes.
Alan Mishchenko
2015-01-26
5
-19
/
+156
|
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-26
1
-28
/
+25
|
*
Experiment with prime computation.
Alan Mishchenko
2015-01-25
1
-0
/
+124
|
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-25
4
-20
/
+71
|
*
Fix in deriving the init values for Wlc_Ntk_t.
Alan Mishchenko
2015-01-22
1
-0
/
+2
|
*
Bug fix in &cone (not able to extract the last PO).
Alan Mishchenko
2015-01-22
1
-1
/
+1
|
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
2
-2
/
+2
|
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
4
-7
/
+72
|
*
Organizing commands for barbuf-aware flow.
Alan Mishchenko
2015-01-20
4
-17
/
+52
|
*
Word-level extension of Cba_Ntk_t.
Alan Mishchenko
2015-01-18
7
-36
/
+91
|
*
Several small bug fixes.
Alan Mishchenko
2015-01-17
4
-2
/
+10
|
*
Organizing commands for barbuf-aware flow.
Alan Mishchenko
2015-01-17
12
-156
/
+411
|
*
Compiler warnings.
Alan Mishchenko
2015-01-16
2
-3
/
+2
|
*
Organizing commands for barbuf-aware flow.
Alan Mishchenko
2015-01-16
11
-163
/
+606
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-15
5
-32
/
+59
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-15
3
-4
/
+1
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-15
7
-442
/
+467
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-13
9
-111
/
+178
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-13
6
-111
/
+577
|
*
Various transformations of Cba_Ntk_t.
Alan Mishchenko
2015-01-11
8
-371
/
+692
|
*
Changing memory model of Cba_Ntk_t.
Alan Mishchenko
2015-01-10
8
-65
/
+75
|
*
Implementation of CE extraction for multiple MUXes driving D-inputs of FFs.
Alan Mishchenko
2015-01-08
2
-51
/
+51
|
*
Returning multiple counter-examples.
Alan Mishchenko
2015-01-03
1
-1
/
+2
|
*
Returning multiple counter-examples.
Alan Mishchenko
2015-01-03
2
-10
/
+45
|
*
Computing polynomials for AIGs representing arithmetic functions.
Alan Mishchenko
2015-01-01
1
-0
/
+227
|
*
Gate sizing with barrier buffers.
Alan Mishchenko
2014-12-21
6
-1
/
+123
|
*
Exprimental features in tech-mapping.
Alan Mishchenko
2014-12-21
1
-110
/
+142
|
*
Exprimental features in tech-mapping.
Alan Mishchenko
2014-12-21
4
-11
/
+71
|
*
Bug fix in reading box library.
Alan Mishchenko
2014-12-20
1
-1
/
+1
|
*
Simplifying AIG with barrier buffers.
Alan Mishchenko
2014-12-19
4
-6
/
+151
|
*
Bug fix in 'testcex' when flop count in the CEX is different from the ↵
Alan Mishchenko
2014-12-19
1
-1
/
+1
|
|
|
|
network (say, after seq synthesis).
*
Bug fix in 'testcex' when flop count in the CEX is different from the ↵
Alan Mishchenko
2014-12-19
1
-2
/
+3
|
|
|
|
network (say, after seq synthesis).
*
Incorrect assertion added by recent changes.
Alan Mishchenko
2014-12-19
1
-1
/
+1
|
*
Induced bug with in DFS computation.
Alan Mishchenko
2014-12-16
1
-1
/
+1
|
*
Commenting out assertions in the mapper, which do not work for barrier buffers.
Alan Mishchenko
2014-12-14
1
-4
/
+4
|
*
Compiler warnings.
Alan Mishchenko
2014-12-13
1
-5
/
+5
|
*
Several additional files for source control.
Alan Mishchenko
2014-12-13
3
-10
/
+6539
|
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-13
4
-17
/
+185
|
*
Adding relax ratio to &synch2.
Alan Mishchenko
2014-12-13
2
-6
/
+19
|
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-13
1
-21
/
+124
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