iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	New hierarchy manager.	Alan Mishchenko	2012-01-13	2	-0/+445
*	Added model ID inside the design.	Alan Mishchenko	2012-01-12	2	-0/+3
*	Bug fix related to not properly resizing SAT solver's model array.	Alan Mishchenko	2012-01-12	2	-0/+2
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-11	6	-202/+566
*	Gate level abstraction.	Alan Mishchenko	2012-01-11	1	-109/+627
*	Gate level abstraction.	Alan Mishchenko	2012-01-08	2	-59/+305
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-08	1	-5/+31
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-07	1	-9/+13
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-07	1	-13/+12
*	Crash fix in 'tempor' in case the leading length is 0.	Alan Mishchenko	2012-01-07	1	-0/+6
*	Gate level abstraction.	Alan Mishchenko	2012-01-07	1	-238/+78
*	Bug fix: changing output number to 0 in the CEX after ORing POs.	Alan Mishchenko	2012-01-07	1	-0/+3
*	Bug fix related to not properly resizing SAT solver's model array.	Alan Mishchenko	2012-01-06	11	-151/+45
*	Added warning when the network from file has no primary inputs.	Alan Mishchenko	2012-01-06	1	-0/+5
*	APIs to represent simple gates in CNF.	Alan Mishchenko	2012-01-05	1	-0/+112
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-05	3	-217/+250
*	APIs to represent simple gates in CNF.	Alan Mishchenko	2012-01-05	1	-0/+100
*	Configuration changes in the Boolean matching code.	Alan Mishchenko	2012-01-05	1	-1/+1
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-01	1	-0/+442
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-01	4	-13/+479
*	Delay optimization using precomputed library.	Alan Mishchenko	2011-12-30	1	-4/+11
*	Delay optimization using precomputed library.	Alan Mishchenko	2011-12-30	1	-1/+3
*	Delay optimization using precomputed library.	Alan Mishchenko	2011-12-30	1	-29/+29
*	Delay optimization using precomputed library.	Alan Mishchenko	2011-12-30	1	-5/+80
*	Delay optimization using precomputed library.	Alan Mishchenko	2011-12-29	6	-186/+1072
*	New variable-time frame abstraction.	Alan Mishchenko	2011-12-29	3	-8/+523
*	Experiments with flattening hierarchy.	Alan Mishchenko	2011-12-28	1	-27/+274
*	Transforming the solver to use different clause representation.	Alan Mishchenko	2011-12-23	3	-38/+83
*	Transforming the solver to use different clause representation.	Alan Mishchenko	2011-12-23	3	-91/+45
*	Transforming the solver to use different clause representation.	Alan Mishchenko	2011-12-23	2	-4/+4
*	Transforming the solver to use different clause representation.	Alan Mishchenko	2011-12-23	11	-543/+2489
*	Transforming the solver to use different clause representation.	Alan Mishchenko	2011-12-22	2	-144/+144
*	Added switch -n to 'miter' to ignore PI/PO names.	Alan Mishchenko	2011-12-22	1	-3/+15
*	Computing interpolants as truth tables.	Alan Mishchenko	2011-12-22	10	-6/+837
*	Improvements to hierarchical BLIF parser.	Alan Mishchenko	2011-12-22	1	-4/+6
*	Improvements to hierarchical BLIF parser.	Alan Mishchenko	2011-12-21	1	-7/+34
*	Fixed a bug in matching code.	Alan Mishchenko	2011-12-17	2	-2/+5
*	Added utility to sort lines in a file alphabetically.	Alan Mishchenko	2011-12-17	1	-0/+97
*	Performance improvement in 'dch' for designs having nodes with many fanouts.	Alan Mishchenko	2011-12-15	1	-28/+56
*	Added optional printout of the hierarchy structure before collapsing.	Alan Mishchenko	2011-12-15	1	-0/+1
*	Undoing temporary change to the solver.	Alan Mishchenko	2011-12-15	1	-1/+1
*	Temporary change to the solver.	Alan Mishchenko	2011-12-15	1	-1/+1
*	Adding switch '-W' to fx to control the quality of extracted divisors.	Alan Mishchenko	2011-12-15	1	-1/+1
*	Adding switch '-W' to fx to control the quality of extracted divisors.	Alan Mishchenko	2011-12-15	4	-15/+41
*	Trying to make sorting of nodes platform-indendent.	Alan Mishchenko	2011-12-15	1	-1/+1
*	Enabling balance again.	Alan Mishchenko	2011-12-15	1	-0/+5
*	Temporarily disabling balance.	Alan Mishchenko	2011-12-15	1	-1/+1
*	Additional print-outs in dc2.	Alan Mishchenko	2011-12-15	1	-10/+10
*	Trying to make sorting of nodes platform-indendent.	Alan Mishchenko	2011-12-15	6	-0/+30
*	Trying to make sorting of nodes platform-indendent.	Alan Mishchenko	2011-12-15	1	-0/+5