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* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-253-11/+11
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* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-254-10/+145
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* Adding new NPN code (compiler fix).Alan Mishchenko2018-03-251-9/+9
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* Adding new NPN code (compiler fix).Alan Mishchenko2018-03-251-1/+1
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* Adding new NPN code developed by XueGong Zhou at Fudan University.Alan Mishchenko2018-03-254-144/+1098
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* Updating &mfs to support hard objects.Alan Mishchenko2018-03-232-2/+55
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* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-226-16/+36
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* Temporary bug fix for signal names in WLC (correction).Alan Mishchenko2018-03-211-2/+5
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* Temporary bug fix for signal names in WLC.Alan Mishchenko2018-03-211-0/+2
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* Bug fix in blasting with boxes.Alan Mishchenko2018-03-061-1/+1
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* Extending primitives supported by WLC.Alan Mishchenko2018-03-033-5/+85
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* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-286-1/+20
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* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-2812-101/+307
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* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-245-5/+113
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* Bug fix in NDR handling.Alan Mishchenko2018-02-201-6/+38
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* Merge two branches.Alan Mishchenko2018-02-201-33/+81
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| * Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
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* | Small fix in satoko.Bruno Schmitt2018-02-202-3/+1
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* Compilation problem with pow().Alan Mishchenko2018-02-194-7/+7
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* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
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* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-112-0/+20
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* Experiments with LUT mapping.Alan Mishchenko2018-02-103-14/+65
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* Fixing input swapping issue in MUXes derived from NDR.Alan Mishchenko2018-02-072-0/+4
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-052-3/+2
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-054-66/+219
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* Suggested fix to compile on FreeBSD.Alan Mishchenko2018-02-041-1/+3
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* Adding support of reading and writing designs using a new internal format ↵Alan Mishchenko2018-01-291-18/+76
| | | | (bug fix).
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-285-5/+364
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-276-5/+1309
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-258-18/+59
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-235-6/+146
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* Updates to exact synthesis commands.Alan Mishchenko2018-01-221-1/+0
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* Updates to exact synthesis commands.Alan Mishchenko2018-01-194-38/+226
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* Backing up node's truth-table to make sure it is not destroyed while ↵Alan Mishchenko2018-01-191-2/+4
| | | | deriving AIG.
* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
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* Merged in Fatsie/abc/liberty_value_expression (pull request #87)Alan Mishchenko2018-01-051-0/+12
|\ | | | | | | Allow expression in value in liberty file
| * Value of properties can be expression.Staf Verhaegen2018-01-031-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Example found in the 2007.03 Liberty Reference Manual that was also found in the wild: input_voltage(CMOS) { vil : 0.3 * VDD ; vih : 0.7 * VDD ; vimin : -0.5 ; vimax : VDD + 0.5 ; } Current implementation just parses the expression but no interpretation is done.
* | New command 'testexact'.Alan Mishchenko2018-01-041-2/+2
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* | New command 'testexact'.Alan Mishchenko2018-01-042-7/+348
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-303-33/+97
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-0/+2
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-287-15/+1336
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* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
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* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
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* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
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