iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	New hierarchy manager.	Alan Mishchenko	2012-01-20	1	-7/+13
*	New hierarchy manager.	Alan Mishchenko	2012-01-19	1	-5/+195
*	New hierarchy manager.	Alan Mishchenko	2012-01-19	2	-21/+29
*	Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control B...	Alan Mishchenko	2012-01-19	5	-20/+48
*	New hierarchy manager.	Alan Mishchenko	2012-01-19	1	-6/+32
*	Added switch 'write_counter -f' to output flop values in each time frame.	Alan Mishchenko	2012-01-18	3	-20/+84
*	New hierarchy manager.	Alan Mishchenko	2012-01-18	1	-2/+36
*	New hierarchy manager.	Alan Mishchenko	2012-01-18	1	-4/+133
*	Removing debug print-outs from the SAT solver.	Alan Mishchenko	2012-01-17	1	-2/+2
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-17	5	-31/+367
*	New hierarchy manager.	Alan Mishchenko	2012-01-17	3	-10/+162
*	Small bug induced by changes in the SAT solver.	Alan Mishchenko	2012-01-17	1	-0/+2
*	Added notification about exceeding the number of nodes.	Alan Mishchenko	2012-01-17	1	-0/+2
*	New hierarchy manager.	Alan Mishchenko	2012-01-17	2	-48/+219
*	Variable timeframe abstraction.	Alan Mishchenko	2012-01-16	1	-211/+159
*	New hierarchy manager.	Alan Mishchenko	2012-01-16	1	-0/+216
*	Removing additional printout in the GIA package.	Alan Mishchenko	2012-01-16	1	-15/+5
*	New hierarchy manager plus additional printout in the GIA package.	Alan Mishchenko	2012-01-16	5	-11/+34
*	Variable timeframe abstraction.	Alan Mishchenko	2012-01-16	3	-132/+274
*	Variable timeframe abstraction.	Alan Mishchenko	2012-01-15	7	-169/+535
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-15	1	-1/+44
*	Several small bug fixes in the mapper.	Alan Mishchenko	2012-01-15	3	-4/+7
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-14	1	-2/+1
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-14	3	-48/+142
*	Bug fixes in the Verilog parser.	Alan Mishchenko	2012-01-14	4	-6/+16
*	New hierarchy manager.	Alan Mishchenko	2012-01-14	4	-57/+160
*	Support computation experiments with different network data-structures.	Alan Mishchenko	2012-01-14	3	-0/+127
*	Small bug fix in printing DSD for Boolean functions.	Alan Mishchenko	2012-01-14	1	-1/+1
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	3	-10/+53
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	3	-19/+18
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	4	-1/+63
*	Improving printout in the SAT solver.	Alan Mishchenko	2012-01-13	2	-2/+4
*	Commented out a printout line which cases a warning to be printed.	Alan Mishchenko	2012-01-13	1	-1/+1
*	Added bit vector.	Alan Mishchenko	2012-01-13	2	-0/+580
*	Added counting hits and misses during structural hashing.	Alan Mishchenko	2012-01-13	4	-2/+10
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	1	-3/+12
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	2	-31/+206
*	Added new name manager and modified hierarchy manager to use it.	Alan Mishchenko	2012-01-13	6	-82/+761
*	New hierarchy manager.	Alan Mishchenko	2012-01-13	2	-0/+445
*	Added model ID inside the design.	Alan Mishchenko	2012-01-12	2	-0/+3
*	Bug fix related to not properly resizing SAT solver's model array.	Alan Mishchenko	2012-01-12	2	-0/+2
*	Changes to the lazy man's synthesis code.	Alan Mishchenko	2012-01-11	6	-202/+566
*	Gate level abstraction.	Alan Mishchenko	2012-01-11	1	-109/+627
*	Gate level abstraction.	Alan Mishchenko	2012-01-08	2	-59/+305
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-08	1	-5/+31
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-07	1	-9/+13
*	Backward reachability using circuit cofactoring.	Alan Mishchenko	2012-01-07	1	-13/+12
*	Crash fix in 'tempor' in case the leading length is 0.	Alan Mishchenko	2012-01-07	1	-0/+6
*	Gate level abstraction.	Alan Mishchenko	2012-01-07	1	-238/+78
*	Bug fix: changing output number to 0 in the CEX after ORing POs.	Alan Mishchenko	2012-01-07	1	-0/+3