| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | New hierarchy manager. | Alan Mishchenko | 2012-01-20 | 1 | -7/+13 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-19 | 1 | -5/+195 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-19 | 2 | -21/+29 |
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| * | Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control ↵ | Alan Mishchenko | 2012-01-19 | 5 | -20/+48 |
| | | | | | BMC frames and conflicts. | ||||
| * | New hierarchy manager. | Alan Mishchenko | 2012-01-19 | 1 | -6/+32 |
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| * | Added switch 'write_counter -f' to output flop values in each time frame. | Alan Mishchenko | 2012-01-18 | 3 | -20/+84 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-18 | 1 | -2/+36 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-18 | 1 | -4/+133 |
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| * | Removing debug print-outs from the SAT solver. | Alan Mishchenko | 2012-01-17 | 1 | -2/+2 |
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| * | Changes to the lazy man's synthesis code. | Alan Mishchenko | 2012-01-17 | 5 | -31/+367 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-17 | 3 | -10/+162 |
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| * | Small bug induced by changes in the SAT solver. | Alan Mishchenko | 2012-01-17 | 1 | -0/+2 |
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| * | Added notification about exceeding the number of nodes. | Alan Mishchenko | 2012-01-17 | 1 | -0/+2 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-17 | 2 | -48/+219 |
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| * | Variable timeframe abstraction. | Alan Mishchenko | 2012-01-16 | 1 | -211/+159 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-16 | 1 | -0/+216 |
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| * | Removing additional printout in the GIA package. | Alan Mishchenko | 2012-01-16 | 1 | -15/+5 |
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| * | New hierarchy manager plus additional printout in the GIA package. | Alan Mishchenko | 2012-01-16 | 5 | -11/+34 |
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| * | Variable timeframe abstraction. | Alan Mishchenko | 2012-01-16 | 3 | -132/+274 |
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| * | Variable timeframe abstraction. | Alan Mishchenko | 2012-01-15 | 7 | -169/+535 |
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| * | Changes to the lazy man's synthesis code. | Alan Mishchenko | 2012-01-15 | 1 | -1/+44 |
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| * | Several small bug fixes in the mapper. | Alan Mishchenko | 2012-01-15 | 3 | -4/+7 |
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| * | Changes to the lazy man's synthesis code. | Alan Mishchenko | 2012-01-14 | 1 | -2/+1 |
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| * | Changes to the lazy man's synthesis code. | Alan Mishchenko | 2012-01-14 | 3 | -48/+142 |
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| * | Bug fixes in the Verilog parser. | Alan Mishchenko | 2012-01-14 | 4 | -6/+16 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-14 | 4 | -57/+160 |
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| * | Support computation experiments with different network data-structures. | Alan Mishchenko | 2012-01-14 | 3 | -0/+127 |
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| * | Small bug fix in printing DSD for Boolean functions. | Alan Mishchenko | 2012-01-14 | 1 | -1/+1 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 3 | -10/+53 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 3 | -19/+18 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 4 | -1/+63 |
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| * | Improving printout in the SAT solver. | Alan Mishchenko | 2012-01-13 | 2 | -2/+4 |
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| * | Commented out a printout line which cases a warning to be printed. | Alan Mishchenko | 2012-01-13 | 1 | -1/+1 |
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| * | Added bit vector. | Alan Mishchenko | 2012-01-13 | 2 | -0/+580 |
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| * | Added counting hits and misses during structural hashing. | Alan Mishchenko | 2012-01-13 | 4 | -2/+10 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 1 | -3/+12 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 2 | -31/+206 |
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| * | Added new name manager and modified hierarchy manager to use it. | Alan Mishchenko | 2012-01-13 | 6 | -82/+761 |
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| * | New hierarchy manager. | Alan Mishchenko | 2012-01-13 | 2 | -0/+445 |
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| * | Added model ID inside the design. | Alan Mishchenko | 2012-01-12 | 2 | -0/+3 |
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| * | Bug fix related to not properly resizing SAT solver's model array. | Alan Mishchenko | 2012-01-12 | 2 | -0/+2 |
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| * | Changes to the lazy man's synthesis code. | Alan Mishchenko | 2012-01-11 | 6 | -202/+566 |
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| * | Gate level abstraction. | Alan Mishchenko | 2012-01-11 | 1 | -109/+627 |
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| * | Gate level abstraction. | Alan Mishchenko | 2012-01-08 | 2 | -59/+305 |
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| * | Backward reachability using circuit cofactoring. | Alan Mishchenko | 2012-01-08 | 1 | -5/+31 |
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| * | Backward reachability using circuit cofactoring. | Alan Mishchenko | 2012-01-07 | 1 | -9/+13 |
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| * | Backward reachability using circuit cofactoring. | Alan Mishchenko | 2012-01-07 | 1 | -13/+12 |
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| * | Crash fix in 'tempor' in case the leading length is 0. | Alan Mishchenko | 2012-01-07 | 1 | -0/+6 |
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| * | Gate level abstraction. | Alan Mishchenko | 2012-01-07 | 1 | -238/+78 |
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| * | Bug fix: changing output number to 0 in the CEX after ORing POs. | Alan Mishchenko | 2012-01-07 | 1 | -0/+3 |
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index : iCE40/abc | |
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