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* Merged in grigora/abc/grigora/fixed-hang-issue-in-bm-command-1413034154897 (p...Alan Mishchenko2014-10-111-7/+6
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| * Fixed "bm" command hang issue.grigora2014-10-111-7/+6
* | MUX decomposition during mapping.Alan Mishchenko2014-10-112-26/+121
* | Deriving network in terms of programmable cells.Alan Mishchenko2014-10-112-6/+14
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* Improvements to the parser.Alan Mishchenko2014-10-101-7/+86
* Naive (SAT-only) CEC option.Alan Mishchenko2014-10-103-2/+116
* Bug fix in the bit-blaster.Alan Mishchenko2014-10-102-5/+5
* Improvements to ISOP.Alan Mishchenko2014-10-102-5/+7
* Improvements to ISOP.Alan Mishchenko2014-10-104-283/+795
* Correction to the patch to compile with Visual Studio.Alan Mishchenko2014-10-101-1/+1
* Suggested patch for type-punned warningsAlan Mishchenko2014-10-105-12/+35
* Small changes.Alan Mishchenko2014-10-082-8/+10
* Compiler warnings.Alan Mishchenko2014-10-082-2/+2
* Compiler warnings.Alan Mishchenko2014-10-081-1/+1
* Compiler warnings.Alan Mishchenko2014-10-083-2/+4
* Detection of threshold functions.Alan Mishchenko2014-10-089-65/+544
* New ISOP computation.Alan Mishchenko2014-10-071-36/+196
* Bug fix in move_names.Alan Mishchenko2014-10-051-0/+1
* Updates to &flow and &flow2.Alan Mishchenko2014-10-051-9/+9
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-042-3/+15
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-049-38/+217
* New ISOP computation.Alan Mishchenko2014-10-042-0/+522
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-035-2/+69
* Bug fix in Verilog writer.Alan Mishchenko2014-10-021-8/+8
* Adding switch -R to 'if'.Alan Mishchenko2014-10-021-27/+39
* Improvements to bit-blaster.Alan Mishchenko2014-10-012-23/+88
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+1
* Improvements to bit-blaster.Alan Mishchenko2014-09-304-75/+122
* Adding options to &flow.Alan Mishchenko2014-09-292-12/+19
* Adding options to &flow2.Alan Mishchenko2014-09-291-4/+4
* Adding options to &flow2.Alan Mishchenko2014-09-292-9/+14
* Adding options to &flow.Alan Mishchenko2014-09-292-21/+26
* Command to rename files in the same directory.Alan Mishchenko2014-09-281-0/+191
* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-282-2/+2
* Adding features to CNF generation.Alan Mishchenko2014-09-282-8/+18
* Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).Alan Mishchenko2014-09-283-11/+51
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-265-79/+196
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-254-14/+35
* Printing node type statistics.Alan Mishchenko2014-09-241-33/+57
* Printing node type statistics.Alan Mishchenko2014-09-241-10/+10
* Printing node type statistics.Alan Mishchenko2014-09-242-2/+106
* Bug fix in handling MUXes in Verilog parser, induced by recent changes.Alan Mishchenko2014-09-241-0/+2
* Added switch -t to &flow2.Alan Mishchenko2014-09-242-9/+14
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-243-18/+167
* Enables dumping stats into a file.Alan Mishchenko2014-09-232-1/+15
* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-233-10/+50
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-232-8/+28
* Adding switch to enable SOP balancing in '&flow2'.Alan Mishchenko2014-09-212-14/+30
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