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* Bug fix in NDR handling.Alan Mishchenko2018-02-201-6/+38
* Merge two branches.Alan Mishchenko2018-02-201-33/+81
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| * Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
* | Small fix in satoko.Bruno Schmitt2018-02-202-3/+1
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* Compilation problem with pow().Alan Mishchenko2018-02-194-7/+7
* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-112-0/+20
* Experiments with LUT mapping.Alan Mishchenko2018-02-103-14/+65
* Fixing input swapping issue in MUXes derived from NDR.Alan Mishchenko2018-02-072-0/+4
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-052-3/+2
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-054-66/+219
* Suggested fix to compile on FreeBSD.Alan Mishchenko2018-02-041-1/+3
* Adding support of reading and writing designs using a new internal format (bu...Alan Mishchenko2018-01-291-18/+76
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-285-5/+364
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-276-5/+1309
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-258-18/+59
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-235-6/+146
* Updates to exact synthesis commands.Alan Mishchenko2018-01-221-1/+0
* Updates to exact synthesis commands.Alan Mishchenko2018-01-194-38/+226
* Backing up node's truth-table to make sure it is not destroyed while deriving...Alan Mishchenko2018-01-191-2/+4
* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
* Merged in Fatsie/abc/liberty_value_expression (pull request #87)Alan Mishchenko2018-01-051-0/+12
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| * Value of properties can be expression.Staf Verhaegen2018-01-031-0/+12
* | New command 'testexact'.Alan Mishchenko2018-01-041-2/+2
* | New command 'testexact'.Alan Mishchenko2018-01-042-7/+348
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-303-33/+97
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-0/+2
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-287-15/+1336
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
* Adding parameter structure to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-064-143/+165
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-063-0/+17
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-063-0/+9
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-064-3/+39
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-1/+50
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-065-17/+63
* Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-063-31/+74
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-062-8/+39
* New command 'lutexact'.Alan Mishchenko2017-12-053-5/+857
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-053-11/+244
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-037-28/+41
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-032-10/+0
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-022-4/+4
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-023-9/+17
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