From 9bd16029f154903b0ece7206d9ab84e393a5ef18 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Tue, 21 Jul 2015 17:59:07 -0700 Subject: Renaming Cba into Bac. --- src/base/bac/bacWriteVer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/base/bac') diff --git a/src/base/bac/bacWriteVer.c b/src/base/bac/bacWriteVer.c index 83826fe7..45742850 100644 --- a/src/base/bac/bacWriteVer.c +++ b/src/base/bac/bacWriteVer.c @@ -64,7 +64,7 @@ static void Psr_ManWriteVerilogSignal( FILE * pFile, Psr_Ntk_t * p, int Sig ) Psr_ManWriteVerilogConcat( pFile, p, Value ); else assert( 0 ); } -static void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) +void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) { int i, Sig; assert( Vec_IntSize(vSigs) > 0 ); -- cgit v1.2.3