From 956842d9cc321eee3907889b820132e6e2b5ec62 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Tue, 22 Aug 2006 08:01:00 -0700 Subject: Version abc60822 --- src/base/seq/seqFpgaCore.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/base/seq/seqFpgaCore.c') diff --git a/src/base/seq/seqFpgaCore.c b/src/base/seq/seqFpgaCore.c index 79e44caf..c6360363 100644 --- a/src/base/seq/seqFpgaCore.c +++ b/src/base/seq/seqFpgaCore.c @@ -382,7 +382,7 @@ int Seq_FpgaMappingCount_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Vec_Ptr_t * vL if ( SeqEdge == (unsigned)pLeaf ) return 0; // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); @@ -417,7 +417,7 @@ Abc_Obj_t * Seq_FpgaMappingBuild_rec( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk, uns if ( SeqEdge == (unsigned)pLeaf ) return pObj->pCopy; // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); @@ -464,7 +464,7 @@ DdNode * Seq_FpgaMappingBdd_rec( DdManager * dd, Abc_Ntk_t * pNtk, unsigned SeqE if ( SeqEdge == (unsigned)pLeaf ) return Cudd_bddIthVar( dd, i ); // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); @@ -514,7 +514,7 @@ void Seq_FpgaMappingEdges_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_Obj_t * p } } // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); @@ -564,7 +564,7 @@ void Seq_FpgaMappingConnect_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_Obj_t * } } // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); @@ -616,7 +616,7 @@ DdNode * Seq_FpgaMappingConnectBdd_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_ } } // continue unfolding - assert( Abc_NodeIsAigAnd(pObj) ); + assert( Abc_AigNodeIsAnd(pObj) ); // get new sequential edges assert( Lag + Seq_ObjFaninL0(pObj) < 255 ); assert( Lag + Seq_ObjFaninL1(pObj) < 255 ); -- cgit v1.2.3