From 1398de7c46d3b2f4e63a6b10965f1e9f4d62742c Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Mon, 8 Dec 2014 14:10:41 -0800 Subject: Integrating barrier buffers. --- src/base/abc/abc.h | 3 +- src/base/abc/abcCheck.c | 2 ++ src/base/abc/abcDfs.c | 4 +-- src/base/abc/abcFunc.c | 27 +++++++++++++++--- src/base/abc/abcHie.c | 1 + src/base/abc/abcUtil.c | 2 ++ src/base/abci/abc.c | 5 ++++ src/base/abci/abcDar.c | 70 ++++++++++++++++++++++++++++++++++++++++++---- src/base/abci/abcPrint.c | 4 ++- src/base/abci/abcStrash.c | 9 +++--- src/base/abci/abcTiming.c | 7 +++++ src/base/cba/cbaWriteVer.c | 2 +- src/base/wlc/wlcBlast.c | 2 +- 13 files changed, 118 insertions(+), 20 deletions(-) (limited to 'src/base') diff --git a/src/base/abc/abc.h b/src/base/abc/abc.h index eb21b091..6acdedad 100644 --- a/src/base/abc/abc.h +++ b/src/base/abc/abc.h @@ -172,6 +172,7 @@ struct Abc_Ntk_t_ int nObjs; // the number of live objs int nConstrs; // the number of constraints int nBarBufs; // the number of barrier buffers + int nBarBufs2; // the number of barrier buffers // the backup network and the step number Abc_Ntk_t * pNetBackup; // the pointer to the previous backup network int iStep; // the generation number for the given network @@ -356,7 +357,7 @@ static inline int Abc_ObjIsLatch( Abc_Obj_t * pObj ) { return pO static inline int Abc_ObjIsBox( Abc_Obj_t * pObj ) { return pObj->Type == ABC_OBJ_LATCH || pObj->Type == ABC_OBJ_WHITEBOX || pObj->Type == ABC_OBJ_BLACKBOX; } static inline int Abc_ObjIsWhitebox( Abc_Obj_t * pObj ) { return pObj->Type == ABC_OBJ_WHITEBOX;} static inline int Abc_ObjIsBlackbox( Abc_Obj_t * pObj ) { return pObj->Type == ABC_OBJ_BLACKBOX;} -static inline int Abc_ObjIsBarBuf( Abc_Obj_t * pObj ) { assert( Abc_NtkIsMappedLogic(pObj->pNtk) ); return Vec_IntSize(&pObj->vFanins) == 1 && pObj->pData == NULL; } +static inline int Abc_ObjIsBarBuf( Abc_Obj_t * pObj ) { assert( Abc_NtkIsLogic(pObj->pNtk) ); return Vec_IntSize(&pObj->vFanins) == 1 && pObj->pData == NULL; } static inline void Abc_ObjBlackboxToWhitebox( Abc_Obj_t * pObj ) { assert( Abc_ObjIsBlackbox(pObj) ); pObj->Type = ABC_OBJ_WHITEBOX; pObj->pNtk->nObjCounts[ABC_OBJ_BLACKBOX]--; pObj->pNtk->nObjCounts[ABC_OBJ_WHITEBOX]++; } // working with fanin/fanout edges diff --git a/src/base/abc/abcCheck.c b/src/base/abc/abcCheck.c index 99fcae4a..fca3b8dc 100644 --- a/src/base/abc/abcCheck.c +++ b/src/base/abc/abcCheck.c @@ -527,6 +527,8 @@ int Abc_NtkCheckNode( Abc_Ntk_t * pNtk, Abc_Obj_t * pNode ) // the node should have a function assigned unless it is an AIG if ( pNode->pData == NULL ) { + if ( Abc_ObjIsBarBuf(pNode) ) + return 1; fprintf( stdout, "NodeCheck: An internal node \"%s\" does not have a logic function.\n", Abc_ObjNameNet(pNode) ); return 0; } diff --git a/src/base/abc/abcDfs.c b/src/base/abc/abcDfs.c index 4508f334..fb7cd3f6 100644 --- a/src/base/abc/abcDfs.c +++ b/src/base/abc/abcDfs.c @@ -1178,7 +1178,7 @@ int Abc_NtkLevel_rec( Abc_Obj_t * pNode ) if ( pNode->Level < (unsigned)Level ) pNode->Level = Level; } - if ( Abc_ObjFaninNum(pNode) > 0 ) + if ( Abc_ObjFaninNum(pNode) > 0 && !Abc_ObjIsBarBuf(pNode) ) pNode->Level++; return pNode->Level; } @@ -1216,7 +1216,7 @@ int Abc_NtkLevelReverse_rec( Abc_Obj_t * pNode ) if ( pNode->Level < (unsigned)Level ) pNode->Level = Level; } - if ( Abc_ObjFaninNum(pNode) > 0 ) + if ( Abc_ObjFaninNum(pNode) > 0 && !Abc_ObjIsBarBuf(pNode) ) pNode->Level++; return pNode->Level; } diff --git a/src/base/abc/abcFunc.c b/src/base/abc/abcFunc.c index 5891c5bd..d7b22b04 100644 --- a/src/base/abc/abcFunc.c +++ b/src/base/abc/abcFunc.c @@ -136,6 +136,8 @@ int Abc_NtkSopToBdd( Abc_Ntk_t * pNtk ) // convert each node from SOP to BDD Abc_NtkForEachNode( pNtk, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + continue; assert( pNode->pData ); if ( Abc_ObjFaninNum(pNode) > 10 ) { @@ -379,6 +381,8 @@ int Abc_NtkBddToSop( Abc_Ntk_t * pNtk, int fDirect ) vCube = Vec_StrAlloc( 100 ); Abc_NtkForEachNode( pNtk, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + continue; assert( pNode->pData ); bFunc = (DdNode *)pNode->pData; pNode->pNext = (Abc_Obj_t *)Abc_ConvertBddToSop( pManNew, dd, bFunc, bFunc, Abc_ObjFaninNum(pNode), 0, vCube, fMode ); @@ -400,6 +404,8 @@ int Abc_NtkBddToSop( Abc_Ntk_t * pNtk, int fDirect ) // transfer from next to data Abc_NtkForEachNode( pNtk, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + continue; Cudd_RecursiveDeref( dd, (DdNode *)pNode->pData ); pNode->pData = pNode->pNext; pNode->pNext = NULL; @@ -513,7 +519,7 @@ void Abc_NtkLogicMakeDirectSops( Abc_Ntk_t * pNtk ) // check if there are nodes with complemented SOPs fFound = 0; Abc_NtkForEachNode( pNtk, pNode, i ) - if ( Abc_SopIsComplement((char *)pNode->pData) ) + if ( !Abc_ObjIsBarBuf(pNode) && Abc_SopIsComplement((char *)pNode->pData) ) { fFound = 1; break; @@ -530,7 +536,7 @@ void Abc_NtkLogicMakeDirectSops( Abc_Ntk_t * pNtk ) // change the cover of negated nodes vCube = Vec_StrAlloc( 100 ); Abc_NtkForEachNode( pNtk, pNode, i ) - if ( Abc_SopIsComplement((char *)pNode->pData) ) + if ( !Abc_ObjIsBarBuf(pNode) && Abc_SopIsComplement((char *)pNode->pData) ) { bFunc = Abc_ConvertSopToBdd( dd, (char *)pNode->pData, NULL ); Cudd_Ref( bFunc ); pNode->pData = Abc_ConvertBddToSop( (Mem_Flex_t *)pNtk->pManFunc, dd, bFunc, bFunc, Abc_ObjFaninNum(pNode), 0, vCube, 1 ); @@ -620,6 +626,8 @@ int Abc_NtkSopToAig( Abc_Ntk_t * pNtk ) // convert each node from SOP to BDD Abc_NtkForEachNode( pNtk, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + continue; assert( pNode->pData ); pNode->pData = Abc_ConvertSopToAig( pMan, (char *)pNode->pData ); if ( pNode->pData == NULL ) @@ -726,6 +734,7 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk ) { Abc_Obj_t * pNode; Hop_Man_t * pMan; + DdNode * pFunc; DdManager * dd, * ddTemp = NULL; Vec_Int_t * vFanins = NULL; int nFaninsMax, i, k, iVar; @@ -753,7 +762,9 @@ int Abc_NtkAigToBdd( Abc_Ntk_t * pNtk ) // convert each node from SOP to BDD Abc_NtkForEachNode( pNtk, pNode, i ) { - DdNode * pFunc = Abc_ConvertAigToBdd( ddTemp, (Hop_Obj_t *)pNode->pData ); + if ( Abc_ObjIsBarBuf(pNode) ) + continue; + pFunc = Abc_ConvertAigToBdd( ddTemp, (Hop_Obj_t *)pNode->pData ); if ( pFunc == NULL ) { printf( "Abc_NtkAigToBdd: Error while converting AIG into BDD.\n" ); @@ -944,12 +955,18 @@ Gia_Man_t * Abc_NtkAigToGia( Abc_Ntk_t * p ) // find the number of objects nObjs = 1 + Abc_NtkCiNum(p) + Abc_NtkCoNum(p); Abc_NtkForEachNode( p, pNode, i ) - nObjs += Hop_DagSize( (Hop_Obj_t *)pNode->pData ); + nObjs += Abc_ObjIsBarBuf(pNode) ? 1 : Hop_DagSize( (Hop_Obj_t *)pNode->pData ); vMapping = Vec_IntStart( nObjs ); // iterate through nodes used in the mapping vNodes = Abc_NtkDfs( p, 0 ); Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + { + assert( !Abc_ObjFaninC0(pNode) ); + pNode->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanin0(pNode)->iTemp ); + continue; + } Abc_ObjForEachFanin( pNode, pFanin, k ) Hop_ManPi(pHopMan, k)->iData = pFanin->iTemp; pHopObj = Hop_Regular( (Hop_Obj_t *)pNode->pData ); @@ -1068,6 +1085,8 @@ int Abc_NtkMapToSop( Abc_Ntk_t * pNtk ) // update the nodes Abc_NtkForEachNode( pNtk, pNode, i ) { + if ( Abc_ObjIsBarBuf(pNode) ) + continue; pSop = Mio_GateReadSop((Mio_Gate_t *)pNode->pData); assert( Abc_SopGetVarNum(pSop) == Abc_ObjFaninNum(pNode) ); pNode->pData = Abc_SopRegister( (Mem_Flex_t *)pNtk->pManFunc, pSop ); diff --git a/src/base/abc/abcHie.c b/src/base/abc/abcHie.c index dc22930c..32b5d310 100644 --- a/src/base/abc/abcHie.c +++ b/src/base/abc/abcHie.c @@ -271,6 +271,7 @@ void Abc_NtkFlattenLogicHierarchy_rec( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk, in // process the blackbox if ( Abc_NtkHasBlackbox(pNtk) ) { + printf( "Flatting black box \"%s\".\n", pNtk->pName ); // duplicate the blackbox assert( Abc_NtkBoxNum(pNtk) == 1 ); pObj = Abc_NtkBox( pNtk, 0 ); diff --git a/src/base/abc/abcUtil.c b/src/base/abc/abcUtil.c index bf3ce301..9309f1e8 100644 --- a/src/base/abc/abcUtil.c +++ b/src/base/abc/abcUtil.c @@ -340,6 +340,8 @@ double Abc_NtkGetMappedArea( Abc_Ntk_t * pNtk ) TotalArea = 0.0; Abc_NtkForEachNode( pNtk, pObj, i ) { + if ( Abc_ObjIsBarBuf(pObj) ) + continue; // assert( pObj->pData ); if ( pObj->pData == NULL ) { diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c index ab83c9af..9939a54e 100644 --- a/src/base/abci/abc.c +++ b/src/base/abci/abc.c @@ -26396,6 +26396,11 @@ int Abc_CommandAbc9Show( Abc_Frame_t * pAbc, int argc, char ** argv ) Abc_Print( -1, "Abc_CommandAbc9Show(): There is no AIG.\n" ); return 1; } + if ( Gia_ManBufNum(pAbc->pGia) ) + { + Abc_Print( -1, "Abc_CommandAbc9Show(): Cannot show GIA with barrier buffers.\n" ); + return 1; + } pMan = Gia_ManToAigSimple( pAbc->pGia ); Aig_ManShow( pMan, 0, NULL ); Aig_ManStop( pMan ); diff --git a/src/base/abci/abcDar.c b/src/base/abci/abcDar.c index d2b74beb..e00dcb9e 100644 --- a/src/base/abci/abcDar.c +++ b/src/base/abci/abcDar.c @@ -820,6 +820,8 @@ static inline Abc_Obj_t * Abc_NtkFromCellRead( Abc_Ntk_t * p, Vec_Int_t * vCopyL int iObjNew = Vec_IntEntry( vCopyLits, Abc_Var2Lit(i, c) ); if ( iObjNew >= 0 ) return Abc_NtkObj(p, iObjNew); + // opposite phase should be already constructed + assert( 0 ); if ( i == 0 ) pObjNew = c ? Abc_NtkCreateNodeConst1(p) : Abc_NtkCreateNodeConst0(p); else @@ -838,7 +840,7 @@ Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p ) Vec_Int_t * vCopyLits; Abc_Obj_t * pObjNew, * pObjNewLi, * pObjNewLo; Gia_Obj_t * pObj, * pObjLi, * pObjLo; - int i, k, iLit, iFanLit, nDupGates, nCells; + int i, k, iLit, iFanLit, nDupGates, nCells, fNeedConst[2] = {0}; Mio_Cell_t * pCells = Mio_CollectRootsNewDefault( 6, &nCells, 0 ); assert( Gia_ManHasCellMapping(p) ); // start network @@ -867,16 +869,74 @@ Abc_Ntk_t * Abc_NtkFromCellMappedGia( Gia_Man_t * p ) Abc_NtkFromCellWrite( vCopyLits, Gia_ObjId(p, pObjLo), 0, Abc_ObjId( pObjNewLo ) ); Abc_LatchSetInit0( pObjNew ); } + + // create constants + Gia_ManForEachCo( p, pObj, i ) + if ( Gia_ObjFaninId0p(p, pObj) == 0 ) + fNeedConst[Gia_ObjFaninC0(pObj)] = 1; + if ( Gia_ManBufNum(p) ) + Gia_ManForEachBuf( p, pObj, i ) + if ( Gia_ObjFaninId0p(p, pObj) == 0 ) + fNeedConst[Gia_ObjFaninC0(pObj)] = 1; + if ( fNeedConst[0] ) + Abc_NtkFromCellWrite( vCopyLits, 0, 0, Abc_ObjId(Abc_NtkCreateNodeConst0(pNtkNew)) ); + if ( fNeedConst[1] ) + Abc_NtkFromCellWrite( vCopyLits, 0, 1, Abc_ObjId(Abc_NtkCreateNodeConst1(pNtkNew)) ); + // rebuild the AIG Gia_ManForEachCell( p, iLit ) { - assert( Vec_IntEntry(vCopyLits, iLit) == -1 ); - pObjNew = Abc_NtkCreateNode( pNtkNew ); - Gia_CellForEachFanin( p, iLit, iFanLit, k ) + int fSkip = 0; + if ( Gia_ObjIsCellBuf(p, iLit) ) + { + assert( !Abc_LitIsCompl(iLit) ); + // build buffer + pObjNew = Abc_NtkCreateNode( pNtkNew ); + iFanLit = Gia_ObjFaninLit0p( p, Gia_ManObj(p, Abc_Lit2Var(iLit)) ); Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) ); - pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL ); + pObjNew->pData = NULL; // barrier buffer + assert( Abc_ObjIsBarBuf(pObjNew) ); + pNtkNew->nBarBufs2++; + } + else if ( Gia_ObjIsCellInv(p, iLit) ) + { + int iLitNot = Abc_LitNot(iLit); + if ( !Abc_LitIsCompl(iLit) ) // positive phase + { + // build negative phase + assert( Vec_IntEntry(vCopyLits, iLitNot) == -1 ); + assert( Gia_ObjCellId(p, iLitNot) > 0 ); + pObjNew = Abc_NtkCreateNode( pNtkNew ); + Gia_CellForEachFanin( p, iLitNot, iFanLit, k ) + Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) ); + pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLitNot)].pName, NULL ); + Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLitNot), Abc_LitIsCompl(iLitNot), Abc_ObjId(pObjNew) ); + fSkip = 1; + } + else // negative phase + { + // positive phase is available + assert( Vec_IntEntry(vCopyLits, iLitNot) != -1 ); + } + // build inverter + pObjNew = Abc_NtkCreateNode( pNtkNew ); + Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLitNot)) ); + pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[3].pName, NULL ); + } + else + { + assert( Gia_ObjCellId(p, iLit) > 0 ); + pObjNew = Abc_NtkCreateNode( pNtkNew ); + Gia_CellForEachFanin( p, iLit, iFanLit, k ) + Abc_ObjAddFanin( pObjNew, Abc_NtkFromCellRead(pNtkNew, vCopyLits, Abc_Lit2Var(iFanLit), Abc_LitIsCompl(iFanLit)) ); + pObjNew->pData = Mio_LibraryReadGateByName( (Mio_Library_t *)pNtkNew->pManFunc, pCells[Gia_ObjCellId(p, iLit)].pName, NULL ); + } + assert( Vec_IntEntry(vCopyLits, iLit) == -1 ); Abc_NtkFromCellWrite( vCopyLits, Abc_Lit2Var(iLit), Abc_LitIsCompl(iLit), Abc_ObjId(pObjNew) ); + // skip next + iLit += fSkip; } + // connect the PO nodes Gia_ManForEachCo( p, pObj, i ) { diff --git a/src/base/abci/abcPrint.c b/src/base/abci/abcPrint.c index 27b9513e..02c06e65 100644 --- a/src/base/abci/abcPrint.c +++ b/src/base/abci/abcPrint.c @@ -306,7 +306,9 @@ void Abc_NtkPrintStats( Abc_Ntk_t * pNtk, int fFactored, int fSaveBest, int fDum // Abc_Print( 1," var = %5d", Abc_NtkCiNum(pNtk) + Abc_NtkCoNum(pNtk)+Abc_NtkGetMultiRefNum(pNtk) ); } else - Abc_Print( 1," lev =%3d", Abc_NtkLevel(pNtk) ); + Abc_Print( 1," lev = %d", Abc_NtkLevel(pNtk) ); + if ( pNtk->nBarBufs2 ) + Abc_Print( 1," buf = %d", pNtk->nBarBufs2 ); if ( fUseLutLib && Abc_FrameReadLibLut() ) Abc_Print( 1," delay =%5.2f", Abc_NtkDelayTraceLut(pNtk, 1) ); if ( fUseLutLib && Abc_FrameReadLibLut() ) diff --git a/src/base/abci/abcStrash.c b/src/base/abci/abcStrash.c index 4dd6bf50..e4868d7e 100644 --- a/src/base/abci/abcStrash.c +++ b/src/base/abci/abcStrash.c @@ -412,7 +412,6 @@ int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int fAddPos ) ***********************************************************************/ void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, int fAllNodes, int fRecord ) { -// ProgressBar * pProgress; Vec_Ptr_t * vNodes; Abc_Obj_t * pNodeOld; int i; //, clk = Abc_Clock(); @@ -422,13 +421,13 @@ void Abc_NtkStrashPerform( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkNew, int fAllNod vNodes = Abc_NtkDfsIter( pNtkOld, fAllNodes ); //printf( "Nodes = %d. ", Vec_PtrSize(vNodes) ); //ABC_PRT( "Time", Abc_Clock() - clk ); -// pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize ); Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNodeOld, i ) { -// Extra_ProgressBarUpdate( pProgress, i, NULL ); - pNodeOld->pCopy = Abc_NodeStrash( pNtkNew, pNodeOld, fRecord ); + if ( Abc_ObjIsBarBuf(pNodeOld) ) + pNodeOld->pCopy = Abc_ObjChild0Copy(pNodeOld); + else + pNodeOld->pCopy = Abc_NodeStrash( pNtkNew, pNodeOld, fRecord ); } -// Extra_ProgressBarStop( pProgress ); Vec_PtrFree( vNodes ); } diff --git a/src/base/abci/abcTiming.c b/src/base/abci/abcTiming.c index 2b378cf7..5484696a 100644 --- a/src/base/abci/abcTiming.c +++ b/src/base/abci/abcTiming.c @@ -828,6 +828,13 @@ void Abc_NodeDelayTraceArrival( Abc_Obj_t * pNode, Vec_Int_t * vSlacks ) // start the arrival time of the node pTimeOut = Abc_NodeArrival(pNode); pTimeOut->Rise = pTimeOut->Fall = -ABC_INFINITY; + // consider the buffer + if ( Abc_ObjIsBarBuf(pNode) ) + { + pTimeIn = Abc_NodeArrival(Abc_ObjFanin0(pNode)); + *pTimeOut = *pTimeIn; + return; + } // go through the pins of the gate pPin = Mio_GateReadPins((Mio_Gate_t *)pNode->pData); Abc_ObjForEachFanin( pNode, pFanin, i ) diff --git a/src/base/cba/cbaWriteVer.c b/src/base/cba/cbaWriteVer.c index 22819fe1..eb27f055 100644 --- a/src/base/cba/cbaWriteVer.c +++ b/src/base/cba/cbaWriteVer.c @@ -147,7 +147,7 @@ void Cba_PrsWriteVerilogNodes( FILE * pFile, Cba_Ntk_t * p ) Cba_PrsWriteVerilogMux( pFile, p, Cba_ObjFanins(p, i) ); else { - char * pName = Cba_NtkStr(p, Func); + //char * pName = Cba_NtkStr(p, Func); assert( 0 ); } } diff --git a/src/base/wlc/wlcBlast.c b/src/base/wlc/wlcBlast.c index dcdb219c..c135b63e 100644 --- a/src/base/wlc/wlcBlast.c +++ b/src/base/wlc/wlcBlast.c @@ -370,7 +370,7 @@ void Wlc_BlastPower( Gia_Man_t * pNew, int * pNum, int nNum, int * pExp, int nEx { Vec_Int_t * vDegrees = Vec_IntAlloc( nNum ); Vec_Int_t * vResTemp = Vec_IntAlloc( nNum ); - int i, * pDegrees, * pRes = Vec_IntArray(vRes); + int i, * pDegrees = NULL, * pRes = Vec_IntArray(vRes); int k, * pResTemp = Vec_IntArray(vResTemp); Vec_IntFill( vRes, nNum, 0 ); Vec_IntWriteEntry( vRes, 0, 1 ); -- cgit v1.2.3