From 6814c48bb4e748add7e4ebd37f0d4d00312e0c5a Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Wed, 29 Aug 2012 12:43:55 -0700 Subject: Added an API to convert a multi-output PLA into a shared AIG. --- src/base/abc/abcUtil.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ src/base/abci/abc.c | 25 ++-------------- src/base/abci/abcFxu.c | 30 ++++++++++++++++++-- 3 files changed, 107 insertions(+), 25 deletions(-) (limited to 'src/base') diff --git a/src/base/abc/abcUtil.c b/src/base/abc/abcUtil.c index 1a36ee01..5a41b109 100644 --- a/src/base/abc/abcUtil.c +++ b/src/base/abc/abcUtil.c @@ -23,6 +23,7 @@ #include "map/mio/mio.h" #include "bool/dec/dec.h" #include "misc/extra/extraBdd.h" +#include "opt/fxu/fxu.h" ABC_NAMESPACE_IMPL_START @@ -2613,6 +2614,82 @@ void Abc_NtkReverseTopoOrderTest( Abc_Ntk_t * p ) Abc_PrintTime( 1, "Time", clock() - clk ); } +/**Function************************************************************* + + Synopsis [Converts multi-output PLA into an AIG with logic sharing.] + + Description [The first argument is an array of char*-strings representing + individual output of a multi-output PLA. The number of inputs (nInputs) + and the number of outputs (nOutputs) are the second and third arguments. + This procedure returns the AIG manager with the given number of inputs + and outputs representing the PLA as a logic network with sharing. + + For example, if the original PLA is + 1000 10 + 0110 01 + 0011 01 + the individual PLA for each the two outputs should be + 1000 1 + and + 0110 1 + 0011 1 + + Reprsentation in terms of two char*-strings will be: + char * pPlas[2] = { "1000 1\n", "0110 1\n0011 1\n" }; + The call to the procedure may look as follows: + Abc_Ntk_t * pNtkAig = Abc_NtkFromPla( pPlas, 4, 2 );] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Ntk_t * Abc_NtkFromPla( char ** pPlas, int nInputs, int nOutputs ) +{ + Fxu_Data_t Params, * p = &Params; + Abc_Ntk_t * pNtkSop, * pNtkAig; + Abc_Obj_t * pNode, * pFanin; + int i, k; + // allocate logic network with SOP local functions + pNtkSop = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_SOP, 1 ); + pNtkSop->pName = Extra_FileNameGeneric("pla"); + // create primary inputs/outputs + for ( i = 0; i < nInputs; i++ ) + Abc_NtkCreatePi( pNtkSop ); + for ( i = 0; i < nOutputs; i++ ) + Abc_NtkCreatePo( pNtkSop ); + Abc_NtkAddDummyPiNames( pNtkSop ); + Abc_NtkAddDummyPoNames( pNtkSop ); + // create internal nodes + for ( i = 0; i < nOutputs; i++ ) + { + pNode = Abc_NtkCreateNode( pNtkSop ); + Abc_NtkForEachPi( pNtkSop, pFanin, k ) + Abc_ObjAddFanin( pNode, pFanin ); + pNode->pData = Abc_SopRegister( (Mem_Flex_t *)pNtkSop->pManFunc, pPlas[i] ); + Abc_ObjAddFanin( Abc_NtkPo(pNtkSop, i), pNode ); + // check that the number of inputs is the same + assert( Abc_SopGetVarNum((char*)pNode->pData) == nInputs ); + } + if ( !Abc_NtkCheck( pNtkSop ) ) + fprintf( stdout, "Abc_NtkFromPla(): Network check has failed.\n" ); + // perform fast_extract + Abc_NtkSetDefaultParams( p ); + Abc_NtkFastExtract( pNtkSop, p ); + Abc_NtkFxuFreeInfo( p ); + // convert to an AIG + pNtkAig = Abc_NtkStrash( pNtkSop, 0, 1, 0 ); + Abc_NtkDelete( pNtkSop ); + return pNtkAig; +} +void Abc_NtkFromPlaTest() +{ + char * pPlas[2] = { "1000 1\n", "0110 1\n0011 1\n" }; + Abc_Ntk_t * pNtkAig = Abc_NtkFromPla( pPlas, 4, 2 ); + Io_WriteBlifLogic( pNtkAig, "temp.blif", 0 ); + Abc_NtkDelete( pNtkAig ); +} + //////////////////////////////////////////////////////////////////////// /// END OF FILE /// //////////////////////////////////////////////////////////////////////// diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c index d3e3357d..0a395574 100644 --- a/src/base/abci/abc.c +++ b/src/base/abci/abc.c @@ -3447,23 +3447,10 @@ usage: int Abc_CommandFastExtract( Abc_Frame_t * pAbc, int argc, char ** argv ) { Abc_Ntk_t * pNtk = Abc_FrameReadNtk(pAbc); - Fxu_Data_t * p = NULL; + Fxu_Data_t Params, * p = &Params; int c; - extern int Abc_NtkFastExtract( Abc_Ntk_t * pNtk, Fxu_Data_t * p ); - extern void Abc_NtkFxuFreeInfo( Fxu_Data_t * p ); - - // allocate the structure - p = ABC_CALLOC( Fxu_Data_t, 1 ); // set the defaults - p->nSingleMax = 20000; - p->nPairsMax = 30000; - p->nNodesExt = 10000; - p->WeightMax = 0; - p->fOnlyS = 0; - p->fOnlyD = 0; - p->fUse0 = 0; - p->fUseCompl = 1; - p->fVerbose = 0; + Abc_NtkSetDefaultParams( p ); Extra_UtilGetoptReset(); while ( (c = Extra_UtilGetopt(argc, argv, "SDNWsdzcvh")) != EOF ) { @@ -3535,29 +3522,22 @@ int Abc_CommandFastExtract( Abc_Frame_t * pAbc, int argc, char ** argv ) goto usage; } } - if ( pNtk == NULL ) { Abc_Print( -1, "Empty network.\n" ); - Abc_NtkFxuFreeInfo( p ); return 1; } - if ( Abc_NtkNodeNum(pNtk) == 0 ) { Abc_Print( -1, "The network does not have internal nodes.\n" ); - Abc_NtkFxuFreeInfo( p ); return 1; } - if ( !Abc_NtkIsLogic(pNtk) ) { Abc_Print( -1, "Fast extract can only be applied to a logic network (run \"renode\").\n" ); - Abc_NtkFxuFreeInfo( p ); return 1; } - // the nodes to be merged are linked into the special linked list Abc_NtkFastExtract( pNtk, p ); Abc_NtkFxuFreeInfo( p ); @@ -3576,7 +3556,6 @@ usage: Abc_Print( -2, "\t-c : use complement in the binary case [default = %s]\n", p->fUseCompl? "yes": "no" ); Abc_Print( -2, "\t-v : print verbose information [default = %s]\n", p->fVerbose? "yes": "no" ); Abc_Print( -2, "\t-h : print the command usage\n"); - Abc_NtkFxuFreeInfo( p ); return 1; } diff --git a/src/base/abci/abcFxu.c b/src/base/abci/abcFxu.c index 9cf2e31a..c50a2bec 100644 --- a/src/base/abci/abcFxu.c +++ b/src/base/abci/abcFxu.c @@ -28,14 +28,40 @@ ABC_NAMESPACE_IMPL_START /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -static int Abc_NtkFxuCheck( Abc_Ntk_t * pNtk ); +static int Abc_NtkFxuCheck( Abc_Ntk_t * pNtk ); static void Abc_NtkFxuCollectInfo( Abc_Ntk_t * pNtk, Fxu_Data_t * p ); static void Abc_NtkFxuReconstruct( Abc_Ntk_t * pNtk, Fxu_Data_t * p ); +extern int Fxu_FastExtract( Fxu_Data_t * pData ); + //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// //////////////////////////////////////////////////////////////////////// +/**Function************************************************************* + + Synopsis [Sets default values of the FXU parameters.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Abc_NtkSetDefaultParams( Fxu_Data_t * p ) +{ + memset( p, 0, sizeof(Fxu_Data_t) ); + p->nSingleMax = 20000; + p->nPairsMax = 30000; + p->nNodesExt = 10000; + p->WeightMax = 0; + p->fOnlyS = 0; + p->fOnlyD = 0; + p->fUse0 = 0; + p->fUseCompl = 1; + p->fVerbose = 0; +} /**Function************************************************************* @@ -190,7 +216,7 @@ void Abc_NtkFxuFreeInfo( Fxu_Data_t * p ) if ( p->vSopsNew ) Vec_PtrFree( p->vSopsNew ); if ( p->vFanins ) Vec_PtrFree( p->vFanins ); if ( p->vFaninsNew ) Vec_PtrFree( p->vFaninsNew ); - ABC_FREE( p ); +// ABC_FREE( p ); } /**Function************************************************************* -- cgit v1.2.3