From 3400670839760fbdee1b18eb3086cc8403eacf72 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Thu, 30 Aug 2012 13:58:26 -0700 Subject: Handling constant nodes in gate sizing. --- src/map/scl/sclLoad.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/map/scl/sclLoad.c') diff --git a/src/map/scl/sclLoad.c b/src/map/scl/sclLoad.c index 686000a9..29f73a60 100644 --- a/src/map/scl/sclLoad.c +++ b/src/map/scl/sclLoad.c @@ -132,7 +132,7 @@ void Abc_SclComputeLoad( SC_Man * p ) pLoad->rise = pLoad->fall = 0.0; } // add cell load - Abc_NtkForEachNode( p->pNtk, pObj, i ) + Abc_NtkForEachNode1( p->pNtk, pObj, i ) { SC_Cell * pCell = Abc_SclObjCell( p, pObj ); Abc_ObjForEachFanin( pObj, pFanin, k ) @@ -147,7 +147,7 @@ void Abc_SclComputeLoad( SC_Man * p ) vWireCaps = Abc_SclFindWireCaps( p ); if ( vWireCaps ) { - Abc_NtkForEachNode( p->pNtk, pObj, i ) + Abc_NtkForEachNode1( p->pNtk, pObj, i ) { SC_Pair * pLoad = Abc_SclObjLoad( p, pObj ); k = Abc_MinInt( Vec_FltSize(vWireCaps)-1, Abc_ObjFanoutNum(pObj) ); -- cgit v1.2.3