From ae46690b066a55d591133f18f75b384abb4bc084 Mon Sep 17 00:00:00 2001 From: Alan Mishchenko Date: Tue, 21 Jul 2015 17:58:23 -0700 Subject: Renaming Cba into Bac. --- src/base/cba/cbaWriteVer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/base/cba/cbaWriteVer.c b/src/base/cba/cbaWriteVer.c index de99458a..58604eb1 100644 --- a/src/base/cba/cbaWriteVer.c +++ b/src/base/cba/cbaWriteVer.c @@ -64,7 +64,7 @@ static void Prs_ManWriteVerilogSignal( FILE * pFile, Prs_Ntk_t * p, int Sig ) Prs_ManWriteVerilogConcat( pFile, p, Value ); else assert( 0 ); } -static void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) +void Prs_ManWriteVerilogArray( FILE * pFile, Prs_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) { int i, Sig; assert( Vec_IntSize(vSigs) > 0 ); -- cgit v1.2.3