blob: 29ce10ddf0777574f52c53fd365d7eca6807b166 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
|
- required time support
- printing ABC version/platform in the output files
- improve AIG rewriting package
- high-effort logic synthesis for hard miters (cofactoring, Boolean division)
- SAT solver with linear constraints
- specialized synthesis for EXORs and large MUXes
- parser for Verilog netlists
- required time based on all cuts
- comparing tts of differently derived the same cut
- area flow based AIG rewriting
- cut frontier adjustment
- box-aware dch, lcorr, and scorr with optional deboxing
- mfs with boxes
- power-aware mapping
- full support of required times
|
