diff options
| -rw-r--r-- | flashchips.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/flashchips.c b/flashchips.c index efe71d87..2f328bb7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -11258,6 +11258,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11292,6 +11303,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11326,6 +11348,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 2000}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11360,6 +11393,17 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + /* + * There is also a volatile lock register per 64KiB sector, which is not + * mutually exclusive with BP-based protection. + */ + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { @@ -11999,6 +12043,13 @@ const struct flashchip flashchips[] = { .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 6, RW}}, + .tb = {STATUS1, 5, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, }, { |