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* Various ichspi.c refinementsFENG yu ning2008-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Corresponding to flashrom svn r367 and coreboot v2 svn r3814. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI ↵FENG yu ning2008-12-081-0/+3
| | | | | | | | | configuration is locked down Corresponding to flashrom svn r364 and coreboot v2 svn r3805. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add AMD SB700 flash enableNiels Ole Salscheider2008-12-051-0/+1
| | | | | | | | | | | This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Corresponding to flashrom svn r361 and coreboot v2 svn r3799. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se>
* Replace #ifdefs for sc520 systems by run time probingStefan Reinauer2008-12-031-0/+56
| | | | | | | | | | Fixes #109 Corresponding to flashrom svn r355 and coreboot v2 svn r3790. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for the AMD/ATI SB600 southbridge SPI functionalityJason Wang2008-11-281-10/+25
| | | | | | | | | | This has been tested by Uwe Hermann on an RS690/SB600 board. Corresponding to flashrom svn r351 and coreboot v2 svn r3779. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Dump ICH8/ICH9/ICH10 SPI registersCarl-Daniel Hailfinger2008-11-031-5/+45
| | | | | | | | | This helps a lot if we have to track down configuration weirdnesses. Corresponding to flashrom svn r338 and coreboot v2 svn r3723. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk2008-10-291-1/+1
| | | | | | | Corresponding to flashrom svn r332 and coreboot v2 svn r3706. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com>
* Add support for the Intel 82371MX (MPIIX) southbridgeUwe Hermann2008-10-281-3/+5
| | | | | | | | | | Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Corresponding to flashrom svn r330 and coreboot v2 svn r3696. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridgesUwe Hermann2008-10-261-1/+7
| | | | | | | | | Tested on PIIX3 hardware. Corresponding to flashrom svn r329 and coreboot v2 svn r3694. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com>
* Add support for the VIA VT82C586A/B chipset, improve documentationUwe Hermann2008-10-251-1/+4
| | | | | | | Corresponding to flashrom svn r328 and coreboot v2 svn r3693. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Coding-style fixes for flashrom, partly indent-aidedUwe Hermann2008-10-181-48/+61
| | | | | | | Corresponding to flashrom svn r326 and coreboot v2 svn r3669. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Allow the SiS 620 chipset to detect and read at least 256kb chipsUrja Rannikko2008-10-181-0/+11
| | | | | | | | | | Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Corresponding to flashrom svn r325 and coreboot v2 svn r3668. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se>
* SB600 has four write once LPC ROM protect areasMarc Jones2008-10-151-0/+21
| | | | | | | | | | | | It is not possible to write enable that area once the register is set so print a warning. Corresponding to flashrom svn r324 and coreboot v2 svn r3659. Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add ICH10 supportCarl-Daniel Hailfinger2008-10-101-0/+10
| | | | | | | | | | The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash interfaces, so this just adds the required PCI IDs. Corresponding to flashrom svn r323 and coreboot v2 svn r3648. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se>
* Recognize the Intel EP80579 LPC flash interfaceEd Swierk2008-08-201-0/+1
| | | | | | | Corresponding to flashrom svn r310 and coreboot v2 svn r3532. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Adding support for flashing system with Nvidia MCP67Stefan Reinauer2008-07-051-0/+1
| | | | | | | Corresponding to flashrom svn r298 and coreboot v2 svn r3414. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* First attempt to clean up SPI probing and create a common construct: the ↵Stefan Reinauer2008-06-301-49/+95
| | | | | | | | | | | | | | | | | | flash bus At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* This patch adds support for VIA SPI controller on VT8237SRudolf Marek2008-06-301-0/+20
| | | | | | | | | It is similar with few documented exceptions to ICH7 SPI controller. Corresponding to flashrom svn r282 and coreboot v2 svn r3398. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se>
* Fix ICH7 non-SPI that broke in r3393Peter Stuge2008-06-291-0/+2
| | | | | | | | | | | | r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Corresponding to flashrom svn r280 and coreboot v2 svn r3395. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Multiple unrelated changesStefan Reinauer2008-06-271-4/+41
| | | | | | | | | | | | * ICH7 SPI support * fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Corresponding to flashrom svn r278 and coreboot v2 svn r3393. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se>
* A bunch of cosmetic improvementsUwe Hermann2008-05-221-1/+1
| | | | | | | | | | | - Fix typos and inconsistencies. - Drop duplicate line which tells us the chip name twice. - Also print the chip vendor, not only the name. Corresponding to flashrom svn r249 and coreboot v2 svn r3348. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Changes to make flashrom compile (and work) on FreeBSDAndriy Gapon2008-05-221-29/+29
| | | | | | | | | | | | This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Corresponding to flashrom svn r245 and coreboot v2 svn r3344. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* ICH8 and ICH9 have an almost identical SPI interface, only the location of ↵Carl-Daniel Hailfinger2008-05-161-10/+16
| | | | | | | | | | | the SPIBAR differs Add ICH8 support to the ICH9 code. Corresponding to flashrom svn r241 and coreboot v2 svn r3327. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add support for SPI chips on ICH9Dominik Geyer2008-05-161-1/+1
| | | | | | | | | This is done by using the generic SPI interface. Corresponding to flashrom svn r239 and coreboot v2 svn r3325. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add more infrastructure for flashrom ICH9 supportCarl-Daniel Hailfinger2008-05-141-25/+42
| | | | | | | Corresponding to flashrom svn r234 and coreboot v2 svn r3314. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add the Intel 6300ESB as known chipset to the chipset struct enablesClaus Gindhart2008-05-141-0/+1
| | | | | | | Corresponding to flashrom svn r233 and coreboot v2 svn r3310. Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Enable ROM decode range to 1MB for vt8237rBari Ari2008-04-291-0/+3
| | | | | | | Corresponding to flashrom svn r220 and coreboot v2 svn r3275. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add ICH9 detectionCarl-Daniel Hailfinger2008-03-181-1/+8
| | | | | | | | | Straight from the datasheet, untested. Corresponding to flashrom svn r215 and coreboot v2 svn r3167. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsetsCarl-Daniel Hailfinger2008-03-141-9/+62
| | | | | | | | | | | | | | Functionality (except printing) should be unchanged. Corresponding to flashrom svn r207 and coreboot v2 svn r3144. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Ward says: This code detects the ICH8 chipset on my laptop, and it appears to use SPI. Acked-by: Ward Vandewege <ward@gnu.org>
* Also print the chip vendor name in --list-supported outputUwe Hermann2008-03-131-49/+50
| | | | | | | | | | | | Cosmetic changes in some files, partly bending the 80-characters-per-line rule in this special case, as the 80-character-limited version looks equally crappy even in an 80x25 console/xterm, so let's make it at least look good in a high-resolution xterm. Corresponding to flashrom svn r203 and coreboot v2 svn r3139. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Add --list-supported option which lists the supported ROM chips, chipsets, ↵Uwe Hermann2008-03-121-2/+12
| | | | | | | | | and mainboards Corresponding to flashrom svn r199 and coreboot v2 svn r3133. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org>
* Further cleanups to enable_flash_cs5536Mart Raudsepp2008-02-111-5/+2
| | | | | | | | | | | | | | | | - Remove the "enable write to flash" message, as the caller appears to already report that. - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as we get an error there already. - Rename a perror string from "read" to "read msr", as we use the latter already in this function for another read. Corresponding to flashrom svn r195 and coreboot v2 svn r3101. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Improve error handling and make RCONF_DEFAULT_MSR address be a constantMart Raudsepp2008-02-081-26/+52
| | | | | | | | | Also, move a big code comment to the top of enable_flash_cs5536(). Corresponding to flashrom svn r193 and coreboot v2 svn r3098. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Write enable flash chips attached to CS3 of CS5536 chipsets (AMD Geode)Mart Raudsepp2008-02-081-12/+33
| | | | | | | | | | | | | | | | This implements support for devices using AMD Geode companion chip CS5536 that have the Boot ROM on NOR flash that is directly connected to FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the NORF_CTL MSR register for flashrom to be able to write to it, including JEDEC probe commands. This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on the DBE61. Corresponding to flashrom svn r192 and coreboot v2 svn r3097. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Correctly disable the ROM area Write Protect bit in the Geode LXMarc Jones2008-01-261-1/+1
| | | | | | | | | | Corresponding to flashrom svn r188 and coreboot v2 svn r3078. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Tested on the pcengines alix1c and works fine. Acked-by: Ronald G. Minnich <rminnich@gmail.com>
* Various coding style fixes, constification, fixed typosUwe Hermann2007-12-041-82/+59
| | | | | | | | | | Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Corresponding to flashrom svn r162 and coreboot v2 svn r2997. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Flashrom support for AMD Geode CS5536Lane Brooks2007-11-131-0/+55
| | | | | | | | | | Attached is a patch that enables AMD Geode CS5536 chipset support. I have tested it successfully on a MSM800 board from digital logic. Corresponding to flashrom svn r160 and coreboot v2 svn r2967. Signed-off-by: Lane Brooks <lbrooks@mit.edu> Acked-by: Jordan Crouse <jordan.crouse@amd.com>
* Add support for Intel 440MX and Fujitsu MBM29F400TCUwe Hermann2007-10-301-0/+1
| | | | | | | | | Detection and reading works, writing is not tested. Corresponding to flashrom svn r158 and coreboot v2 svn r2903. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se>
* Some cosmetic cleanups in the flashrom code and outputUwe Hermann2007-10-171-2/+2
| | | | | | | Corresponding to flashrom svn r151 and coreboot v2 svn r2873. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix wrong values/typos in chipset_enable.cCarl-Daniel Hailfinger2007-10-171-2/+2
| | | | | | | | | | This has been confirmed by Ed Swierk in http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html . Corresponding to flashrom svn r150 and coreboot v2 svn r2868. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Revert my last cleanup patchUwe Hermann2007-10-101-1/+1
| | | | | | | Corresponding to flashrom svn r143 and coreboot v2 svn r2847. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Cosmetic changes to make the flashrom output more consistentUwe Hermann2007-10-101-1/+1
| | | | | | | Corresponding to flashrom svn r142 and coreboot v2 svn r2846. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Change out/in combinations to pci_read/write_byte in sis630 chipset enableAlex Beregszaszi2007-09-111-6/+4
| | | | | | | Corresponding to flashrom svn r138 and coreboot v2 svn r2770. Signed-off-by: Alex Beregszaszi <alex@rtfs.hu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Change all flashrom license headers to use our standard formatUwe Hermann2007-08-291-7/+19
| | | | | | | | | No changes in content of the files. Corresponding to flashrom svn r131 and coreboot v2 svn r2751. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Cosmetic fixesUwe Hermann2007-08-231-9/+8
| | | | | | | Corresponding to flashrom svn r130 and coreboot v2 svn r2748. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Drop a bunch of useless header files, merge them into flash.hUwe Hermann2007-08-231-2/+0
| | | | | | | Corresponding to flashrom svn r128 and coreboot v2 svn r2746. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Fix up and document the AMD CS5530/CS5530A supportUwe Hermann2007-06-061-10/+21
| | | | | | | | | | | | | The previous code was pretty unreadable, undocumented and did some totally unrelated things (such as mucking with the game port or port 0x92). This version is tested with a 256 KB chip and should work for the CS5530 and CS5530A. Corresponding to flashrom svn r120 and coreboot v2 svn r2715. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Document the newly supported IBM x3455 board and the now-supported Broadcom ↵Uwe Hermann2007-06-051-4/+3
| | | | | | | | | HT-1000 chipset Corresponding to flashrom svn r119 and coreboot v2 svn r2713. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
* Move GPIO settings to board specific code for IBM x3455Stefan Reinauer2007-06-051-5/+0
| | | | | | | Corresponding to flashrom svn r118 and coreboot v2 svn r2712. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
* Add support for BCM HT1000 chipsetStefan Reinauer2007-06-051-0/+24
| | | | | | | | | Tested on IBM x3455. Corresponding to flashrom svn r117 and coreboot v2 svn r2711. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de>
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