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* flashchips: Remove FEATURE_4BA_WREN for MT25QL128 and mark as testedRick Altherr2023-01-151-2/+2
| | | | | | | | | | | | | | | | | Using both a Dediprog SF100 and a Bus Pirate, read and erase works correctly on a MT25QL128 but writes were failing to take effect. Currently, the entry in flashchips.c indicates that this device supports 4-byte addressing. Micron's datasheet indicates that it does not. After removing FEATURE_4BA_WREN from feature_bits, both SF100 and Bus Pirate were able to successfully read, erase, and write a MT25QL128 so also marking as tested. Change-Id: I6341456c722840a413bd2c51fe9a78bbda5cdbab Signed-off-by: Rick Altherr <kc8apf@kc8apf.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: Mark W25Q128.V WP as testedEdward O'Callaghan2022-12-191-1/+1
| | | | | | | | | | | | BUG=b:258755442 TEST=`-p internal --wp-status`. Change-Id: Ifbd5ee76f2087764ab8841ca96de6990cb31260d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70866 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add WP settings for Flash Chip `W25Q512NW`Subrata Banik2022-12-161-2/+13
| | | | | | | | | | | | | | | | | This patch adds WP register bits and decode range for Flash Chip `W25Q512NW`. TEST=Able to flash AP FW, wp-enable/disable on Google/rex device which has flash chip `W25Q512NW`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic5148f71404466dcf7772e3eb6e1800eb8666696 Reviewed-on: https://review.coreboot.org/c/flashrom/+/67827 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* flashchips.c: Indent definition of W25Q512NW-IM properlyFelix Singer2022-12-161-40/+40
| | | | | | | | Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Icfd2a49383da0f8f0a4e3295aba81ce1d200652c Reviewed-on: https://review.coreboot.org/c/flashrom/+/68151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* flashchips.c: remove WREN from GD25Q256D enter 4BA sequenceNikolai Artemiev2022-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As noted in a comment on `commit 86fc9cf7ab221bc54ef6f10252e296fc2d7a22d2`, the GD25Q256D datasheet indicates that the chip does not require a WREN command to enter 4BA mode. Testing has confirmed that a WREN command is not required, so change the flashchip feature flags from FEATURE_4BA_WREN to FEATURE_4BA. Ticket: https://ticket.coreboot.org/issues/356 BUG=none BRANCH=none TEST=read/write/erase/verify GD25Q256D flash with FT2232H programmer TEST=called spi_enter_exit_4ba(true), dumped registers, checked ADS=1. Change-Id: I96e48933f33c52c0d10a0d4cb7f7e07c1fceab99 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Add 4BA write to XM25Qx256CLiam Flaherty2022-12-011-2/+3
| | | | | | | | | | | | | | | | | | | Flash chips XM25QH256C and XM25QU256C support the 4-byte program command (0x12) according to their datasheets, but the feature flag is not enabled in flashchips.c, so enable it to allow this feature to be used. TICKET: https://ticket.coreboot.org/issues/371 BUG=b:259493706 TEST=build Change-Id: I96c80762fcda2af6028c7a53d8c545b0c6565cbd Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69713 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert flashchips db to use indirection for printlockNikolai Artemiev2022-11-231-408/+408
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip printlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: Icff868d9454e9b0a059a736457bb562430436033 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchips db to use indirection for unlockEdward O'Callaghan2022-11-231-421/+421
| | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip unlock func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I3ed51142cd22becc8286959f5504565158fa2de0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashchips.c: enable WP for 7 entries of MX chipsSergii Dmytruk2022-11-191-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These weren't split: * MX25L3206E/MX25L3208E Tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6405 * MX25L6405D * MX25L6406E/MX25L6408E Tested: https://github.com/Dasharo/flashrom/pull/8 MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F was split into: * MX25L6436E/MX25L6445E/MX25L6465E - security register - WPS - tested: https://github.com/Dasharo/flashrom/pull/8 * MX25L6473E - security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - WPS * MX25L6473F - NO security register - OTP TB bit in CONFIG/STATUS2 (0x15 opcode) - NO WPS Change-Id: Ib3db9d39ffacd3e9e44de92c6cfb6c3ecc8615bd Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for MT25QL512, N25Q0{32,64}..{1,3}ESergii Dmytruk2022-11-191-0/+51
| | | | | | | | Change-Id: Ib0f3cb9516cea7bb678842a358a82099221e1ed9 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66215 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: enable WP for W25Q32.V, W25Q32.W and W25Q32JW...MSergii Dmytruk2022-11-191-6/+248
| | | | | | | | | | | | Split chips: * W25Q32.V -> W25Q32BV/W25Q32CV/W25Q32DV, W25Q32FV and W25Q32JV * W25Q32.W -> W25Q32BW/W25Q32CW/W25Q32DW, W25Q32FW and W25Q32JW...Q Change-Id: Id259c27dfa6c681bbadc73b3bd7559ad6a5865f4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips.c: enable WP for EN25QH32 and EN25QH64Sergii Dmytruk2022-11-191-0/+96
| | | | | | | | | | | | | | | Split chips: * EN25QH32 -> EN25QH32 and EN25QH32B * EN25QH64 -> EN25QH64 and EN25QH64A Unlike older revisions both newly added EN25QH32B and EN25QH64A support half block (32KiB) erase operation via 0x52 opcode. Change-Id: I759f0119346235ce0bddc78cde9c461495990c25 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert flashchips db to use indirection for erase_blockEdward O'Callaghan2022-11-111-1938/+1938
| | | | | | | | | | | | | | This paves the way to allow for the conversion of flashchip erase_block func ptr to enumerate values. This change should be a NOP. TEST=`diff -u <(objdump -D flashchips.o_bk) <(objdump -D flashchips.o)`. Change-Id: I122295ec9add0fe0efd27273c9725e5d64f6dbe2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69131 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add write protect bits to W25Q64JW...MEvan Benn2022-11-101-1/+12
| | | | | | | | | | | | | | | https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW BUG=b:245996788 BRANCH=None TEST=None Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62 Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* tree/: Convert flashchip read func ptr to enumerateEdward O'Callaghan2022-11-011-587/+587
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I612d46fefedf2b69e7e2064aa857fa0756efb4e7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66788 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip write func ptr to enumerateEdward O'Callaghan2022-11-011-589/+589
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I80149de169464b204fb09f1424a86fc645b740fd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip probe func ptr to enumerateEdward O'Callaghan2022-11-011-592/+592
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I00aaab9c83f305cd47e78c36d9c2867f2b73c396 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip decode range func ptr to enumNikolai Artemiev2022-10-281-22/+22
| | | | | | | | | | | | | | | | | | | | Replace the `decode_range` function pointer in `struct flashchip` to an enum value. The enum value can be used to find the corresponding function pointer by passing it to `lookup_decode_range_func_ptr()`. Removing function pointers like `decode_range` makes it possible to represent chip data in a declarative format that does not have to be stored as C source code. BUG=b:242479049 BRANCH=none TEST=ninja && ninja test Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6d08d414d3d1ddadc95ca1d407fc87c23ab543d Reviewed-on: https://review.coreboot.org/c/flashrom/+/67195 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark WP of 9 entries as testedSergii Dmytruk2022-10-231-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on information from: * commit a850fd0aa8054a1125a9231fa3317428f15900f4 - GD25LQ128C/GD25LQ128D/GD25LQ128E - GD25LQ64(B) - GD25Q127C/GD25Q128C - GD25Q256D/GD25Q256E - GD25Q64(B) * commit a8204dd34d90ac9ab2783e1dd486ec781d4c0dba - GD25Q32(B) * commit 7b4c4f36113c4b7ed5c985d4cf51733639e69bf8 - W25Q64BV/W25Q64CV/W25Q64FV * https://github.com/Dasharo/dasharo-issues/issues/67 - W25Q128.V..M * https://github.com/Dasharo/flashrom/pull/8 - W25Q64.W Change-Id: I090188bad568885f78778e7fc7d8dbe20fb2445f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: Kamil Pokornicki <kamil.pokornicki@3mdeb.com> Tested-by: Przemyslaw Banasiak <przemyslaw.banasiak@3mdeb.com> Tested-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68180 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark MT25QU256 as testedAngel Pons2022-07-051-1/+1
| | | | | | | | | | | | As reported by Charles Parent on the mailing list. Change-Id: I9d8b0038673185103ba08c9797ff94f2f7639d6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62664 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: change GD25Q256D to "GD25Q256D/GD25Q256E"Nikolai Artemiev2022-07-051-1/+1
| | | | | | | | | | | | | | | | Extend "D" chip entry to include newer "E" parts. BUG=b:234054642 BRANCH=none TEST=builds Change-Id: I6b398d417da9289cc1d6a191fb20e3f937addb21 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Add missing block eraser for S25FL512SNico Huber2022-06-231-0/+3
| | | | | | | | | | | | | Now that we can make use of the extended-address register, we can also advertise the `d8` eraser that can take 3- or 4-byte addresses. Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/357 Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64637 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for S25FL512SNico Huber2022-06-231-2/+3
| | | | | | | | | | | | | | | | According to its datasheet, Spansion S25FL512S supports writing/ reading its extended address register via 0x17/0x16 opcodes. With that enabled, we can also enable the EAR7 feature, i.e. toggling 4BA mode via bit 7 of that register. S25FL512S did not advertise EAR support at all, so we set it to TEST_UNTESTED again. Change-Id: Ib214e509a5c294ab60460a2b5d00a713a119ab3f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Enable FEATURE_4BA_EAR_1716 for ISSI chipsNico Huber2022-06-231-2/+4
| | | | | | | | | | | | | | | | | According to their datasheets, ISSI IS25LP256 and IS25WP256 support both 0xc5/0xc8 and 0x17/0x16 opcodes to write / read their extended address register. Flashrom will use 0xc5 by default if available, so adding the FEATURE_4BA_EAR_1716 flag makes no difference for now (FEATURE_4BA_EAR_C5C8 is included in the already selected FEATURE_4BA set). It's better to have a comprehensive description of the chips, though, in case somebody wants to use them in the future with a master that restricts available opcodes. Change-Id: I03e4ff825c7742e7ff79b51b75293d53a091d4d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716Nico Huber2022-06-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8Nico Huber2022-06-221-3/+3
| | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Drop FOUR_BYTE_ADDR commentsNico Huber2022-06-221-7/+0
| | | | | | | | | | | 4BA support is implemented by now. So drop these obsolete comments. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I28c5d1de052c28735d5f07874874068ee744b77f Reviewed-on: https://review.coreboot.org/c/flashrom/+/64600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Split W25Q256.VNico Huber2022-06-221-1/+56
| | | | | | | | | | | | The W25Q256JV supports the full set of 4BA instructions, including two native-4BA block erasers. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef Ticket: https://ticket.coreboot.org/issues/362 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256LNico Huber2022-06-201-0/+123
| | | | | | | | | | | | | | | | | | | | | | | These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg: Allow WRSR_EXT for Status Register 3Nico Huber2022-06-201-5/+7
| | | | | | | | | | | | | | | | | Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c, flashcips.c: Test the order of erase functionsAarya Chaumal2022-06-201-12/+12
| | | | | | | | | | | | | | | | | | Add a check so that the erase functions for all flashchips are in increasing order of their respective eraseblock sizes. This is required for the implentation of the improved erasing algorithm. The patch uses the count of eraseblocks in each erase function to determine the order (More eraseblocks means that the function has smaller eraseblock size). Also fix the structs in flashchips.c which were found to be not conforming to this test. TEST = make && ./flashrom Change-Id: I137cb40483fa690ecc6c7eaece2d9d3f7a851bb4 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64961 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dummyflasher: Wire variable size feature via opaque infraAnastasia Klimchuk2022-06-161-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire "variable size" feature in dummy programmer via opaque infra. This patch fixes the broken build with CONFIG_DUMMY=no. Dummyflasher registers opaque master for the case when it is initialised with EMULATE_VARIABLE_SIZE. Dummy opaque master emulates read/write/erase as simple memory operations over `data->flashchip_contents`. The feature works via "Opaque flash chip" in flashchips.c which has one block eraser at the moment. If this changes in future, each block eraser needs to be updated in `probe_variable_size`. Fixes: https://ticket.coreboot.org/issues/365 TEST=the following scenarious run successfully Testing build $ make clean && make CONFIG_DUMMY=no $ flashrom -h : dummy is not in the list $ make clean && make CONFIG_EVERYTHING=yes $ flashrom -h : dummy is in the list Testing "variable size" feature $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V $ head -c 8388608 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V also same as above with erase_to_zero=yes Testing standard flow $ flashrom -p dummy:emulate=W25Q128FV -V $ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V $ head -c 16777216 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V Testing invalid combination of programmer params (`init_data` fails and prints error message which is WAI) $ flashrom -p dummy:size=8388608 -V -> init_data: size parameter is only valid for VARIABLE_SIZE chip. $ flashrom -p dummy:emulate=VARIABLE_SIZE -V -> init_data: the size parameter is not given. $ flashrom -p dummy:emulate=W25Q128FV,erase_to_zero=yes -V -> init_data: erase_to_zero parameter is not valid for real chip. Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add W25Q512NW-IM ID to flashromAtul Dhudase2022-06-071-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25Q512NW-IM chip ID and specs to flashrom. BUG=b:200173901 BRANCH=none TEST=flash W25Q512NW-IM using CCD. Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890 Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shelley Chen <shchen@chromium.org> Original-Commit-Queue: Shelley Chen <shchen@chromium.org> (cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61) Note: this commit was cherry-picked from the cros tree but includes corrections to errors in the original commit's 4BA feature flags that were spotted by Angel Pons Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Fix W25Q256.WPatrick Rudolph2022-05-261-3/+8
| | | | | | | | | | | | | | | | | The JW is the only known variant. A W25Q256FW may have existed with less 4BA instructions supported, but it never showed up and no data- sheet is available. Used the datasheet from here: https://www.winbond.com/resource-files/w25q256jw%20spi%20revb%2012082017.pdf Change-Id: I9a3995c66ad7b74823e17984bf1ffac50b5663e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Ticket: https://ticket.coreboot.org/issues/362 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* flashchips.c: add CMP bit entry to W25Q256.VNikolai Artemiev2022-05-261-0/+1
| | | | | | | | | | | | | | | Add bit that was missed in `commit a850fd0a` BUG=b:182223106 BRANCH=none TEST=builds Change-Id: I1cb400f6b8542a9054875b8f2557db1cc06292e2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64607 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: enable write-protection for W25Q{64,128}.VSergii Dmytruk2022-05-011-4/+76
| | | | | | | | | | | | | | | | | | | | | Configuration for W25Q64 was tested on hardware (W25Q64FV). Emulation of W25Q128 in dummyflasher will be extended to support WP. Haven't tested this one on hardware, but it's the same configuration as for W25Q64 except that it has WPS. W25Q64JV chip was renamed to W25Q64JV-.M (those with QPI). W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS) and W25Q64JV-.Q (SR3 and WPS, but no QPI). Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: mark IS25LP064 as TEST_OK_PREWSimon Buhrow2022-04-241-1/+1
| | | | | | | | | | | | Tested '-w', '-E' and '-r' successfully with my FT2232H programmer. Change-Id: I2197ce0be9db7c3d74b24c7445dc06238584ffea Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58472 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark GD25Q40(B) as testedSimon Buhrow2022-04-241-1/+1
| | | | | | | | | | | | As mentioned by Wolf Dieter Brandt in his mail from 07.Feb.22. Change-Id: Idec3d82efbdf095c3d57bfe5f0fd487007b554cb Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashchips.c: add writeprotect support for more chipsNikolai Artemiev2022-04-051-14/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chips I had available for testing were tested with all writeprotect commands and an FT232H adapter. Chips I wasn't able to test were just checked against the datasheets. Chips used for testing (including chips added in previous patches) are listed in the table below: Flashrom Chip name | Chip(s) tested ---------------------------------+---------------------------- AT25SL128A | EN25QH128 | GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG GD25LQ64(B) | GD25LQ64CWIG GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG GD25Q256D | GD25Q256DYIG GD25Q64(B) | GD25Q64CSIG W25Q128.JW.DTR | W25Q128.V..M | W25Q128.W | W25Q256JV_M | W25Q256.V | W25Q64.W | XM25QH128C | XM25QH256C | BUG=b:182223106 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips,writeprotect_ranges: add range decoding functionNikolai Artemiev2022-03-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though some will require different functions (e.g. MX25L6406 and related chips). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 BRANCH=none TEST=dumped range tables, checked against datasheets Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flash.h,flashchips.c: add writeprotect bit layout map to chipsNikolai Artemiev2022-03-011-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a register bit map `struct reg_bit_info`, with fields for storing the register, bit index, and writability of each bit that affects the chip's write protection. This allows writeprotect code to be independent of the register layout of any specific chip. The new fields have been filled out for example chips. The representation is centered around describing how bits can be accessed and modified, rather than the layout of registers. This is generally easier to work with in code that needs to access specific bits and typically requires specifying the locations of fewer bits overall. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg,flashchips: add SR2 read/write supportNikolai Artemiev2022-02-281-3/+4
| | | | | | | | | | | | | | | | | | | | | This patch adds support for reading and writing the second status register and enables it on a limited set of flash chips. Chip support for RDSR2/WRSR2/extended WRSR is represented using feature flags to be consistent with how other SPI capabilities are represented. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series TEST=logged SR2 read/write values during wp commands Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Add W25Q64JVSimon Buhrow2021-12-091-0/+40
| | | | | | | | | | I have successfully tested it with FT2232H-programmer. Change-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46 Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips.c: mark EN25F10 as TEST_OK_PREWSimon Buhrow2021-10-011-1/+1
| | | | | | | | | | As reported by Wolf Dieter Brandt in his e-mail from 09.Aug.2021. Change-Id: I0c19f84780e7fa3699fd706f8e105fc5937ba8bf Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add MX25L12833FTao Xia2021-08-241-2/+2
| | | | | | | | | | | | Just add the name to the existing entry, as usual it is supposed to be compatible. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I14ab7e04f5209d2bcf34b0d2de9da2c01bf32d00 Reviewed-on: https://review.coreboot.org/c/flashrom/+/56546 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add 'GD25LQ128E' to match C and D variantsEdward O'Callaghan2021-08-241-1/+1
| | | | | | | | | | | | | | | | | As defined by gigadevice. C, D and E are all meant to be the same. BUG=b:185957191 BRANCH=none TEST=builds Change-Id: I3bef9386a185a0e8c54c125af5509b63540995aa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add MX25L12873FNico Huber2021-07-141-1/+1
| | | | | | | | | | | Just add the name to the existing entry, as usual it is supposed to be compatible. Change-Id: I59c8067f15b5ceac5a2e2f8fe93431a465f17e23 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add support for Macronix MX66L1G45GPatrick Rudolph2021-06-201-0/+49
| | | | | | | | | | Tested on Dediprog SF600: Reading and writing works. Change-Id: I554e828c97d9ec77b08489573a34e176599d2518 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Mark MT25QL256 as testedSimon Buhrow2021-06-101-1/+1
| | | | | | | | | | As mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020. Change-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618 Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: change chip name from 'W25Q64JW' to 'W25Q64JW...M'Nikolai Artemiev2021-06-101-2/+2
| | | | | | | | | | | | | | | | | | | | According to the W25Q64JW datasheet rev. E, only devices ending with the letter 'M' have a device ID of 8017h. There are other variants with different device IDs. This patch makes the 'W25Q64JW...M' definition consistent with the 'W25Q32JW...M' definition. The device ID macro defined in flashchips.h has also been renamed from WINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M. BUG=b:166294558 BRANCH=none TEST=builds Change-Id: Ib0dc914da286a191d22e666332b1063b88db4251 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 02:17:53 +0000