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* spi: Make 'default_spi_write_aai' the default unless definedEdward O'Callaghan2022-12-211-3/+0
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_write_aai' as to not need this explicit specification of 'default'. Therefore Drop the explicit need to specify the 'default_spi_write_aai' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi: Expose flash descriptor regions through get_region()Nikolai Artemiev2022-12-161-4/+72
| | | | | | | | | | | | | | | | | | | | | | | | | Region attributes are now stored in a `fd_regions` array after being decoded in ich9_handle_frap() and used by ich_get_region(). A special cases is handled in ich_get_region(): if there is a gap between two flash regions, an artificial region is created to fill the gap. I.e. any address inside the gap will return a region that spans the gap between the end the of the previous region and the start of the next region. This allows ich_get_region() to be used to iterate the entire flash region-by-region. Read and write operations are assumed to be allowed inside gaps between regions. BUG=b:260440773 BRANCH=none TEST=flashrom -{r,w,E,v} on dedede (JSL) Change-Id: I019f3f407f6a2a82f686a168457e0e32961ff483 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70127 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Read chip ID and use it to populate `flash->chip`Nikolai Artemiev2022-12-161-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | Read the flash chip vendor/device ID using hardware sequencing, find the corresponding flashchip entry, and copy it over to `flash->chip`. Identifying the chip was not previously required as ICH hardware sequencing handles chip-level details related to read/write/erase ops. However writeprotect operations require the chip entry to be identified so that chip->reg_bits can be used to compute status register values. BUG=b:253715389,b:253713774 BRANCH=none TEST=flashrom on dedede (JSL) identifies "W25Q128.V..M" chip TEST=flashrom -{r,v} on dedede TEST=write/erase bios region on dedede: flashrom -{E,w} --layout <(echo '0x381000:0xffffff bios') -i bios Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69195 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Damien Zammit Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi.c: Clean up HSFC FCYCLE definitionsNikolai Artemiev2022-12-151-22/+29
| | | | | | | | | | | | | | | | | | | Move the FCYCLE bit definitions out of the ICH9 definitions and into their own section because they are used by PCH100 as well. Rename HSFC_FCYCLE to ICH9_HSFC_FCYCLE because it is specific to ICH9. BUG=b:253715389,b:253713774 BRANCH=none TEST=builds Change-Id: I0996c5331837276049241600e0ffac21a47ec3af Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* tree/: Rename 'internal_delay()' to 'default_delay()'Edward O'Callaghan2022-12-121-5/+5
| | | | | | | | | | | | | | | The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Replace NULL-case of programmer_delay() with internal_delayEdward O'Callaghan2022-12-121-5/+5
| | | | | | | | | | | | | | Replace `programmer_delay(NULL, [..])` calls with direct `internal_delay([..])` dispatches explicitly. Custom driver delays remain hooked as well as core flashrom logic. The NULL base case of 'programmer_delay()' then becomes a condition to validate for layering violations or invalid flash contexts. Change-Id: I1da230804d5e8f47a6e281feb66f381514dc6861 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68434 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* writeprotect,ichspi,spi25: handle register access constraintsNikolai Artemiev2022-12-061-4/+12
| | | | | | | | | | | | | | | | | | | | | Make the spi25 register read/write functions return SPI_INVALID_OPCODE if the programmer blocks the read/write opcode for the register. Likewise, make ichspi read/write register functions return SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd. Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to read/write SR1, which should always be supported. BUG=b:253715389,b:253713774,b:240229722 BRANCH=none TEST=flashrom --wp-{enable,disable,range,list,status} on dedede Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree/: Make probe_opcode() flashctx argument constNikolai Artemiev2022-12-041-1/+1
| | | | | | | | | | | | | | | | | | | Probing an opcode generally shouldn't involve mutating the flashctx state and currently no probe_opcode functions do that. Make the flashctx arg const so that call sites don't need to have a non-const pointer. BUG=b:253715389,b:253713774 BRANCH=none TEST=ninja test Change-Id: I19e98be50d682de2d2715417f8b7b8c62b871617 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Fix number of bytes for HW seq operationsSubrata Banik2022-11-251-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Clear Fast SPI HSFC register before HW seq operationSubrata Banik2022-11-251-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a regression introduced with commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out common hwseq_xfer logic into helpers). The reason for the regression is ignoring the fact that the Fast SPI controller MMIO register HSFC (0x06) might not hold the default zero value before initiating the HW sequencing operation. Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent a byte that needs to be transfered. While debugging the regression, we have observed that the default value in the FDBC (prior to initiate any operation) is 0x3f (instead of zero) which represents 64-byte transfer. localhost ~ # iotools mmio_read32 0x92d16006 0x3f00 <Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06> FDBC offset during `--wp-disable` operation represents higher numbers of bytes than the actual and eventually results in the error. Additionally, dropped unused variable (struct hwseq_data *hwseq_data). BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. Without this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x3f11 With this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x0 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x11 Additionally, verified other HW sequencing operations (like read, write, erase, read status, write status, read ID) working fine without any error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* opaque_master: Mark Opaque chip as tested for WPAnastasia Klimchuk2022-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Opaque masters, by design, populate the flashchip structure during the execution of their probe function. Therefore any opaque master operation displays a message to the user: "This flash part has status UNTESTED for operations: WP". However, for all the other operations (read, write, erase) opaque masters always mark them as tested. Thus, align WP as marked tested inline with other opaque chip operations. BUG=b:258755442 TEST=the following does not display untested message: 1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE 2) flashrom -p internal (on Intel device) Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATALEdward O'Callaghan2022-11-091-7/+7
| | | | | | | | Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: heap allocate hwseq_data to remove globalEdward O'Callaghan2022-11-031-6/+18
| | | | | | | | | | | | Align hwseq path in ichspi with the rest of the flashrom tree by making hwseq_data a heap allocation within the life-time of the driver managed by the driver registration API. Change-Id: Ib362c5ab2d3e8afee2c3c7d3135cc4414d6bd6c3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: derive hsfc_fcycle from ctx in ich_start_hwseq_xfer()Edward O'Callaghan2022-11-031-1/+2
| | | | | | | | | | | | | Allow helpers to derive driver specific data from the driver specific context instead of being a closure over a static global variable. Change-Id: Ib0ccf4b32fd1e2be2ecc3a4a4c6e397c8e901a0a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ichspi.c: plumb flashctx through hwseq xfer helperEdward O'Callaghan2022-11-031-8/+9
| | | | | | | | | | | | Change is a NOP to prepare ichspi to remove hwseq_data being a global symbol in CB:68774. This allows for the helper functions to derive their data from the driver data context. Change-Id: I67b5aa6350930d912e5036473ac3e792debac0bd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: provide flashrom context into programmer_delay()Alexander Goncharov2022-10-171-5/+5
| | | | | | | | | | | | | | | | | Modify the `programmer_delay` function signature to allow passing the flashrom context. Programmers that depend on internal delay should provide NULL as a context. The use of this function parameter will be introduced in CB:67393. TOPIC=programmer_handle_global TEST=builds Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi: Do not attempt to map physical memory for hwseqJonathon Hall2022-10-081-2/+0
| | | | | | | | | | | | | | | | ICH hwseq does not need to actually mmap flash, and this fails for flash chips >16 MB, since only the top 16 MB is mapped into the address space. Test: Read and write flash on ICH hwseq with 32 MB flash chip. Change-Id: Ie698071c3181e988f10b750b0e50c9700efaa1a3 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68090 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers: Move (un)map_flash_region to par/spi/opaque_masterJonathon Hall2022-10-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Move (un)map_flash_region function pointers from programmer_entry to par_master, spi_master, and opaque_master. This enables programmers to specify a different mapper per bus, which is needed for the internal programmer. Mapping is closely tied to the way the memory is accessed using the other functions in the bus master structs. Validate that FWH/LPC programmers provide specialized mapping in register_par_master(); this is needed for chips with FEATURE_REGISTERMAP, which only exist on FWH or LPC buses. programmer.c: Update comment in fallback_map(), NULL return is the desired behavior. Test: Read firmware on SB600 Promontory mainboard (requires physmap) Test: Read firmware externally with ft2232_spi Test: Read firmware on ICH hwseq, verify physmap still occurs Change-Id: I9c3df6ae260bcdb246dfb0cd8e043919609b014b Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Co-Authored-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Factor out common hwseq_xfer logic into helpersSubrata Banik2022-09-261-90/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Add a unified `execute SPI flash transfer` function that does: - Check the SCIP bit prior initiate new operation. - Start the transfer by setting address and length for transfer, finally set FGO bit. - Wait for the transaction to get completed/failed/timed out. 2. All HW Sequencing SPI operation uses `execute SPI flash transfer` function Note: The refactoring xfer logic here assumes setting `HSFC_FDBC to 0` while performing erase operation using `ich_hwseq_block_erase()`. But it does not impact the erase operations. BUG=b:223630977 TEST=Able to perform read-status/write-status/read/write/erase operation on PCH 600 series chipset (board name: google/kano). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic9fd50841449e02f476a8834f4642d6ecad36dc3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62869 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Retype appropriate variables with boolFelix Singer2022-09-081-10/+11
| | | | | | | | | | | | Use the bool type instead of an integer for appropriate variables, since this represents their purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: If7eeacc44921f52aa593ab1302f17a5c5190f830 Reviewed-on: https://review.coreboot.org/c/flashrom/+/66892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-6/+6
| | | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Also plumb programmer_cfg though get_params. Change-Id: I480589bb50b47fdf5af259d068f49fedfce88ea5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Change signature of extract_programmer_param_str()Edward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | | | | Results can be reproduced with the following invocation; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(/extract_programmer_param_str(NULL, /g' '{}' \; ``` This allows for a pointer to the actual programmer parameters to be passed instead of a global. Change-Id: I781a328fa280e0a9601050dd99a75af72c39c899 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi.c: Clean up get_ich_spi_mode_param()Felix Singer2022-08-241-5/+7
| | | | | | | | | | | | | Instead of checking for the variable arg in multiple compound statements, separate it out in its own branch and return 0 if arg is NULL. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id1038568ff25cf6f0895b26921cc4a0d7bcfabb7 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi.c: Pack hwseq_data into opaque.data fieldEdward O'Callaghan2022-08-241-27/+38
| | | | | | | | | | | | | | | | | | | | | | | The hwseq_data struct remains to be a stack allocated instance for now however it is referenced in the opaque_master data field of the flash ctx. This allows for worker functions that leverage hwseq_data state to derive state indirectly via the flash ctx instead of directly upon the global state. This allows for unblocking further work to finally dispense with the stack allocation in favour of a heap allocation with a defined life-time of the driver. BUG=b:237839418 TEST=builds Change-Id: I2ad57d496176cf26edcd0ba40154cc6250846e33 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi.c: Make ich_hwseq_wait_for_cycle_complete() take addr_mask as argEdward O'Callaghan2022-08-151-8/+8
| | | | | | | | | | | | | | | Move towards functions depending less on globals. BUG=b:237839418 TEST=builds Change-Id: I7c02a33c0984f24efcaff967c496880d70922575 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65204 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi.c: Fix ich_hwseq_get_erase_block_size() type signatureEdward O'Callaghan2022-08-151-6/+6
| | | | | | | | | | | | | | | Move towards functions depending less on globals. BUG=b:237839418 TEST=builds Change-Id: Id1de6eb184340b3cac8a6bdbb94c22c8e37d8d2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Alexander Goncharov <chat@joursoir.net>
* ichspi.c: Let ich_hwseq_set_addr() take addr_mask as a argumentEdward O'Callaghan2022-08-151-9/+9
| | | | | | | | | | | | | | | Move towards functions depending less on globals. BUG=b:237839418 TEST=builds Change-Id: I891119fd9ed528f6b3578b7a84f66f1b058500e1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65202 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Alexander Goncharov <chat@joursoir.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* ichspi: Call `Set Flash Address` API from `Read/Write Status` functionsSubrata Banik2022-07-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch calls into `ich_hwseq_set_addr` function by passing flash address `0` while performing Read and Write status operation as Intel SPI BWG recommends that "SW should program the FADDR every time before any transaction as FADDR is used to determine which Chip Select, CS0 if FADDR <= device 0 size, else CS1". The reason behind setting the flash address in this patch is to adhere to the Intel recommended reference implementation that programs FADDR. Additionally, the followup patch will factor out `hwseq_xfer` logic to create a helper function that ensures all SPI related operational APIs could leverage the common `hwseq_xfer` logic. BUG=b:223630977 TEST=Able to perform read-status/write-status operation on PCH 600 series chipset (board name: google/kano). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib1d85ebdde99a31728f404d66a1eb4e3599b9054 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65468 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Add function to probe erase command opcode for all spi_masterAarya Chaumal2022-07-111-0/+7
| | | | | | | | | | | | | | | | | | | | Add a field, probe_opcode, to struct spi_master which points to a function returning a bool by checking if a given command is supported by the programmer in use. This is used for getting a whitelist of commands supported by the programmer, as some programmers like ichspi don't support all opcodes. Most programmers use the default function, which just returns true. ICHSPI and dummyflasher use their specialized function. Change-Id: I6852ef92788221f471a859c879f8aff42558d36d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-021-1/+1
| | | | | | | | | | | | | This patch changes the function name of extract_programmer_param() to extract_programmer_param_str() as this function name will clearly specify that it returns the value of the given parameter as a string. Signed-off-by: Chinmay Lonkar <chinmay20220@gmail.com> Change-Id: Id7b9fff4d3e1de22abd31b8123a1d237cd0f5c97 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tree: indent struct *_master consistently with tabsThomas Heijligen2022-06-271-29/+29
| | | | | | | | | | | | | | Use `<tab>.key<tab>*= <value>,` TEST: `make VERSION=0 MAN_DATE=0` returns the same flashrom binary before and after the patch Change-Id: I1c45ea9804ca09e040d7ac98255042f58b01f8ef Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: Simplify ich9_handle_{frap,pr}() to work with logical repEdward O'Callaghan2022-06-241-26/+21
| | | | | | | | | | | | | | Simplify ich9_handle_frap() to do the translation to the logical representation of the ich_access_protection enum in one place and work from there. This removes some unnecessary branch complexity and the possibility of out of bounds array accesses. Change-Id: I1eda067c44a84d662713475d13902c85534a59fe Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65189 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
* ichspi.c: Implement read_write_status for wpEdward O'Callaghan2022-06-211-0/+74
| | | | | | | | | | | | | | | | | The ichspi hwseq path has a opaque master specialisation that allows for reading and writing STATUS1 registers. Hook the callbacks with a implementation to allow for this so that writeprotect maybe supported though this path. BUG=none BRANCH=none TEST=flashrom --wp-status on AMD and Intel DUTs Change-Id: I7ecbe8491ecea3697922c91af26ca62276e86317 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-031-1/+1
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macrosSubrata Banik2022-05-031-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces useful macros (read/write/erase) and uses these macros throughout the SPI operations. Additionally, implicitly using the HSFC_CYCLE_READ macro for the SPI read operation. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Additionally, no difference in flashrom binary seen while comparing flashrom binary generated with CB:62888 and between CB:62888 to CB:62868 below: flashrom$ cmp flashrom flashrom_old <<none>> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62868 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi: Introduce HSFC_FDBC_VAL(n) macroSubrata Banik2022-05-031-2/+3
| | | | | | | | | | | | | | | This patch introduces HSFC_FDBC_VAL(n) macro to use in SPI read and write operations. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Introduce HSFC_FCYCLE_MASK(n) macroSubrata Banik2022-05-031-2/+21
| | | | | | | | | | | | | | | This patch introduces HSFC_FCYCLE_MASK(n) macro to cover both ICH and PCH hardware sequencing FCYCLE Bit width. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Reviewed-on: https://review.coreboot.org/c/flashrom/+/62891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ichspi: Drop unused `_pprint_reg` macroSubrata Banik2022-05-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch drops `_pprint_reg` macro as `pprint_reg` macro is now able to call into msg_pdbg(). BUG=b:223630977 TEST=Able to display HSFS register offset properly as below BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000) 0x04: 0xf000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offsetSubrata Banik2022-05-031-1/+1
| | | | | | | | | | | | | | | | This patch uses `pprint_reg` macro instead `_pprint_reg` with explicit register name and offset macros being passed as argument. BUG=b:223630977 TEST=Able to display PCH100_HSFC.FCYCLE offset properly. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macrosSubrata Banik2022-05-031-3/+3
| | | | | | | | | | | | | | | | | | | | This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Unify timeouts across all SPI operations to 30sSubrata Banik2022-04-271-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument in favor of a fixed timeout of `30 seconds` for any given SPI operation as recommended by the SPI programming guide. Document: Alder Lake-P Client Platform SPI Programming Guide Rev 1.30 (supporting document for multi-master accessing the SPI Flash device.) Refer to below section to understand the problem in more detail and SPI operation timeout recommendation from Intel in multi-master scenarios. On Intel Chipsets that support multi-mastering access of the SPI flash may run into a timeout failure when the operation initiated from a single master just follows the SPI operational timeout recommendation as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR specification, table 9.7). In the multi-master SPI accessing scenario using hardware sequencing operation, it's impossible to know the actual status of the SPI bus prior to individual master starting the operation (SPI Cycle In Progress a.k.a SCIP bit represents the status of SPI operation on individual master). Thus, any SPI operation triggered in multi-master environment might need to account a worst case scenario where the most time consuming operation might have occupied the SPI bus from a master and an operation initiated by another master just timed out. Here is the timeout calculation for any hardware sequencing operation: Worst Case Operational Delay = (Maximum Time consumed by a SPI operation + Any marginal adjustment) Timeout Recommendation for Hardware Sequencing Operation = ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + Current Operational latency) Assume, on Intel platform with 6 SPI master like, Host CPU, CSE, EC, GbE and other reserved etc, hence, the Timeout Calculation for SPI erase Operation would look like as below: Maximum Time consumed by a SPI Operation = 5 seconds Worst Case Operational Delay = 5 seconds Timeout Recommendation for Hardware Seq Operation = 5 seconds * (6 - 1) + 5 seconds = 30 seconds BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Reviewed-on: https://review.coreboot.org/c/flashrom/+/62867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sam McNally <sammc@google.com>
* ichspi.c: Check SPI Cycle In-Progress prior start HW SeqSubrata Banik2022-03-091-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit. Software must initiate the next SPI transaction when this bit is 0. Platform Setup: Alder Lake based ChromeOS devices (Brya variants) Replication Steps: Accepting and running firmware Auto Update (AU) on the Brya variants (dogfooder system) is seeing `flashrom` getting timed out. Problem Statement: Evidencing AU (Auto Update) failure while performing firmware update on the Alder Lake based ChromeOS devices. Observation: Based on the initial understanding from the failure log/pattern, it seems like the platform is evidencing multiple `flashrom` access from different source, for example: `futility` accesses flashrom for erase, write and read operation, `crossystem` uses flashrom for updating VBNV, additionally, `set_fw_good` script also uses `crossystem` to update the fw status. Solution: Without this SCIP check being implemented in flashrom, there is no way to ensure multiple instances of flashrom performing different SPI operations are not cancelling each other and running into below error: Erasing and writing flash chip... Timeout error between offset 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED! Uh oh. Erase/write failed. Checking if anything has changed. TEST=Able to flash coreboot image on Alder Lake (Brya variants), Tiger Lake (Volteer variants), Kaby Lake (Eve system), Comet Lake (Hatch variants) and Ivybridge without any failure. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib9265cc20513fd00f32f8fa22e28c312903ca484 Reviewed-on: https://review.coreboot.org/c/flashrom/+/61854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Does exactly what it says on the tin. BUG=b:220799648 TEST=```localhost ~ # flashrom --flash-name <snip> Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. vendor="Programmer" name="Opaque flash chip" flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom flashrom unknown on Linux 5.15.22 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). coreboot table found at 0x768a7000. Found chipset "Intel Alder Lake-N". Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPI Configuration is locked down. OK. Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading ich descriptor... done. Using regions: "bios", "fd". Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000 /dev/mem mmap failed: Resource temporarily unavailable Could not map flash chip W25Q256JV_M at 0x00000000fe000000. Reading flash... done. SUCCESS Also, Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset '600 series Alder Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00500000 - 01ffffff named bios Added layout entry 00001000 - 004fffff named me ``` Tested on Nivviks/ADL-N and Brya/ADL-P. Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sam McNally <sammc@google.com>
* Add Elkhart Lake supportWerner Zeh2022-02-041-2/+11
| | | | | | | | | | | | | | | | Elkhart Lake has a chipset called Mule Creek Canyon which is quite compatible with 300 series chipsets. There are a few differences though, e.g. different encoding for the SPI clock values for read and write in the FLCOMP register. In addition Elkhart Lake has a new PCI device ID for the SPI controller which is added, too. TEST=Read and flash complete flash on Siemens MC EHL1 Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Remove unneeded line breaks, add useful line breaks and tabsAnastasia Klimchuk2022-02-021-58/+36
| | | | | | | | | | | | | | | | BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) flashrom binary built before and after this patch with command `make clean && make CONFIG_EVERYTHING=yes VERSION=none` is the same Change-Id: I7ca2902b7caaa95418b828b068c661afafdcd171 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/60272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Extract initialisation of swseq and hwseq into a functionAnastasia Klimchuk2022-02-021-34/+41
| | | | | | | | | | | | | | | | | | | | | | | | Initialisation of swseq_data and hwseq_data gets its own function, which is called from init_ich_default. This makes init_ich_default more readable. This patch also gives a name to (previously anonymous) struct swseq_data. Its sibling struct hwseq_data already has a name. Structs need names to be able to declare function parameters. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3 Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Extract handling programmer param into a functionAnastasia Klimchuk2022-02-021-27/+37
| | | | | | | | | | | | | | | | | | | | | Extract processing of ich_spi_mode into a separate function which is called from init_ich_default. This makes init_ich_default more readable and avoids one local variable. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976 Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Split very long init function into twoAnastasia Klimchuk2022-02-021-242/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ich_init_spi is very long, but logically it can be split. Init function detects the chipset and then the rest of operations depends on the chipset. Init function is more readable now, it consists of only a switch. Initialisation of hwseq and swseq that used to happen in the beginning of init function now moved to init_ich_default, because hwseq and swseq are only used for chipsets served by init_ich_default. BUG=b:204488958 TEST=Check that the following scenarios still behave properly: 1) probe-read-verify-erase section-write-reboot on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E 2) probe and read on Panther Point (7 series PCH) 3) on machine with ich7 chipset, output from probe and read is the same between master and this patch Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: Nico Huber <nico.h@gmx.de> Tested-by: Nicholas Chin <nic.c3.14@gmail.com> Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58735 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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