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* parallel.c: Consoldiate parallel master registration logicEdward O'Callaghan2022-08-251-0/+1
| | | | | | | | | | | | | | | | This is analogous to spi.c and opaque.c however parallel logic was previously never consoldiated. This free's up flashrom.c from namespace pollution. BUG=b:242246291 TEST=builds with both make and meson. Change-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Move write_buf_to_include_args() to cli_classic.cEdward O'Callaghan2022-08-251-1/+0
| | | | | | | | | | | | | | | | | The write_buf_to_include_args() helper is only ever used by the cli frontend therefore make it static local to the user. BUG=b:242246291 TEST=builds Change-Id: Ia16bf4b8e46a011aa45f98089d43904b077833a0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Move read_buf_from_include_args() into cli_classic.cEdward O'Callaghan2022-08-251-1/+0
| | | | | | | | | | | | | | | | | The read_buf_from_include_args() helper is only ever used by the cli frontend therefore make it static local to the user. BUG=b:242246291 TEST=builds Change-Id: I9dee63d67320085e16c64eefb2723169f49f07aa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: flatten out write_buf_to_include_args()Edward O'Callaghan2022-08-251-1/+1
| | | | | | | | | | | | | | | | | | | write_buf_to_include_args() does not need the whole flashctx, rather it works with a fix layout and buffer. Just pass what state is actually required. BUG=b:242246291 TEST=builds Change-Id: I885c4395356eef27746c66300233f07f4718ccdf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66644 Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: flatten out read_buf_from_include_args()Edward O'Callaghan2022-08-251-1/+1
| | | | | | | | | | | | | | | | | | | read_buf_from_include_args() does not need the whole flashctx, rather it works with a fix layout and buffer. Just pass what state is actually required. BUG=b:242246291 TEST=builds Change-Id: Ieadd68895c7ba05cc3d770d304351b02622f14d7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66633 Reviewed-by: Evan Benn <evanbenn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716Nico Huber2022-06-231-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8Nico Huber2022-06-221-5/+6
| | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi25_statusreg: Allow WRSR_EXT for Status Register 3Nico Huber2022-06-201-1/+3
| | | | | | | | | | | | | | | | | Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de>
* tree: Consolidate BIT() macroEdward O'Callaghan2022-06-101-0/+2
| | | | | | | | | Change-Id: I7e61f7671b70ca5ed751d99405714436bcd18d5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* libflashrom: Return progress state to the library userRichard Hughes2022-05-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | Projects using libflashrom like fwupd expect the user to wait for the operation to complete. To avoid the user thinking the process has "hung" or "got stuck" report back the progress complete of the erase, write and read operations. Add a new --progress flag to the CLI to report progress of operations. Include a test for the dummy spi25 device. TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c Signed-off-by: Richard Hughes <richard@hughsie.com> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* include/flash.h: Drop dead struct membersEdward O'Callaghan2022-05-171-2/+0
| | | | | | | | | | | | | These were part of the original wp implementation, now dead code left over. Change-Id: I43b25175c6ff833b822a93c4e752a28cf97d64b8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.c: Make need_erase() helper static localEdward O'Callaghan2022-05-171-1/+0
| | | | | | | | | | | | The need_erase() helper is only used within flashrom.c Change-Id: Ic0946bb109fca2fc18e15eefa11cccea284ded0b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom: Drop read_flash_to_file() usageEdward O'Callaghan2022-05-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspire towards a goal of making cli_classic more of just a user of libflashrom than having quasi-parallel paths in flashrom.c This converts remaining read_flash_to_file() usage to the do_read() provider wrapper around libflashrom. BUG=b:208132085 TEST=` sudo ./flashrom -p ft2232_spi:type=232H,divisor=1000 -f -r out -c W25X05 Flashrom output: No EEPROM/flash device found. Force read (-f -r -c) requested, pretending the chip is there: Assuming Winbond flash chip "W25X05" (64 kB, SPI) on ft2232_spi. Please note that forced reads most likely contain garbage. Block protection could not be disabled! Reading flash... done. Data read: xxd out-1khz 00000000: 0000 07ff ffff e000 0000 7fff fffe 0000 ................ 00000010: 0007 ffff ffe0 0000 007f ffff fe00 0000 ................ 00000020: 07ff ffff e000 0000 7fff fffe 0000 0007 ................ 00000030: ffff ffe0 0000 007f ffff fe00 0000 0fff ................ xxd out-100khz 00000000: b6db 6db6 db6d b6db 6db6 db6d b6db 6db6 ..m..m..m..m..m. 00000010: db6d b6db 6db6 db6d b6db 6db6 db6d b6db .m..m..m..m..m.. 00000020: 6db6 db6d b6db 6db6 db24 9249 2492 4924 m..m..m..$.I$.I$ 00000030: 9249 2492 4924 9249 2492 4924 9249 2492 .I$.I$.I$.I$.I$. ` Change-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-031-2/+2
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-0/+494
Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
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