| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256L | Nico Huber | 2022-06-20 | 1 | -0/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | ||||
| * | Add W25Q512NW-IM ID to flashrom | Atul Dhudase | 2022-06-07 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25Q512NW-IM chip ID and specs to flashrom. BUG=b:200173901 BRANCH=none TEST=flash W25Q512NW-IM using CCD. Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890 Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shelley Chen <shchen@chromium.org> Original-Commit-Queue: Shelley Chen <shchen@chromium.org> (cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61) Note: this commit was cherry-picked from the cros tree but includes corrections to errors in the original commit's 4BA feature flags that were spotted by Angel Pons Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> | ||||
| * | Introduce an `include` directory for header files | Thomas Heijligen | 2022-04-29 | 1 | -0/+1033 |
| Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> | |||||
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