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* tree/: Drop default_spi_probe_opcode for NULL caseEdward O'Callaghan2023-03-031-2/+1
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate as it implies default behaviour of a supported opcode within the `check_block_eraser()` match supported loop. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi: Make default cmd helpers static internalEdward O'Callaghan2023-03-031-3/+0
| | | | | | | | | | | | | | | | | | | | Avoid these leaking into driver implementations as a NULL field now implies their implementation. This removes one source of a driver bug where both `mst->command` AND `mst->multicommand` are set to default implementations which is actually a cyclical control flow condition. The driver however must still have either `mst->command` OR `mst->multicommand` defined and so both cannot be NULL. This simplifies the code and driver development. Change-Id: I4ef95846c2f005cf4aa727f31548c6877d2d4801 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ch347_spi: Add initial support for the WCH CH347Nicholas Chin2023-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Add support for the WCH CH347, a high-speed USB to bus converter supporting multiple protocols interfaces including SPI. Currently only mode 1 (vendor defined communication interface) is supported, mode 2 (USB HID communication interface) support will be added later. The code is currently hard coded to use CS1 and a SPI clock of 15 MHz, though there are 2 CS lines and 6 other GPIO lines available, as well as a configurable clock divisor for up to 60MHz operation. Support for these will be exposed through programmer parameters in later commits. This currently uses the synchronous libusb API. Performance seems to be alright so far, if it becomes an issue I may switch to the asynchronous API. Tested with a MX25L1606E flash chip Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* asm106x: add programmer for ASM106x SATA controllersAlex Badea2023-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | The ASMedia ASM106x series is a PCIe-SATA controller chip. It supports an attached SPI flash chip that can contain configuration and PCI option ROM. The interface is a simple shifter accessed via PCI config space, up to 4 bytes at a time. Add a programmer driver for it. Tested on a G536PCE1061V11 IO-PCE1061-V1.1 PCIe card, and a MPCE2ST-A01 VER006S mini-PCIe card, both with chips marked ASM1061, both enumerate as: 01:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Change-Id: I591b117be911bdb8249247c20530c1cf70f6e70d Signed-off-by: Alex Badea <vamposdecampos@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/73037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* internal: Move parallel logic into internal_par implementationEdward O'Callaghan2023-02-151-1/+2
| | | | | | | | | | | | | The parallel internal programmer is its own implementation. Move it and call into it from the top-level internal.c programmer implementation. Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmers: Allow opaque programmers to specify custom delayEdward O'Callaghan2023-02-011-0/+1
| | | | | | | | | | | | | | | The dummyprogrammer in the opaque case can have a NOP delay to avoid wasting CPU time and energy. BUG=b:266014935 TEST=builds Change-Id: Ia86ad21f011214abc2aa0891a43559f91e2a9591 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/72424 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal,board_enable: Remove force_boardenable from globalsEdward O'Callaghan2023-01-151-4/+3
| | | | | | | | | | | | Make `force_boardenable` stack local to the internal_init() entry-point. It's life-time should not exceed that of the internal's init entry function. Change-Id: I3324681f024003694a5531d9d35bb13d2c583eb0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70031 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer.h: Guard against sending spi commands on non-spi mstEdward O'Callaghan2023-01-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Validate (flash->chip->bustype == BUS_SPI) as ich copies the chip flags in the opaque master and tries incorrectly to issue 4BA commands which results in failure. The issue was detected only in the case of chips >16MB, in this case 'W25Q256FV' that has the feature bits: ``` .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, ``` The regression was noticed from, commit 0741727925b841c2479b993204ce58c5eb75185a ichspi.c: Read chip ID and use it to populate `flash->chip` TEST=In the case of 'W25Q256FV' on TigerLake. Change-Id: I7cce4f9c032d33c01bf616e27a50b9727a40fe1b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Sam McNally <sammc@google.com>
* parallel: Drop explicit fallback_chip_X boilerplateEdward O'Callaghan2023-01-111-6/+0
| | | | | | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => fallback_chip_X' as to not need this explicit specification. Therefore drop the explicit need to specify these fallback callback function pointer in the par_master struct. This is a reasonable default for every driver in the tree. Furthermore, move the 'fallback_chip_X()' func from the generic programmer.c register logic into its relevant home of parallel.c and make static local to clean up link-time symbol space. This simplifies the code and driver development. Change-Id: If25c0048a07057aa72be6ffa8d8ad7f0a568dcf7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71745 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer: Add get_region to spi/opaque mastersNikolai Artemiev2022-12-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a get_region function to spi and opaque masters so that they can expose access permissions for multiple regions within the flash. A get_region() implementation is added for the ichspi driver in a following patch. Finally, another patch uses get_region() to make read_flash() and write_flash() skip inaccessable regions, making read, write, and erase operations work on Intel platforms with active an CSME coprocessor. This logic will be integrated with layout in the future, but for now this moves ichspi support forward without making refactoring too hard later on. BUG=b:260440773 BRANCH=none TEST=ninja test Change-Id: I8c43f6b705f36ef18842a04ba6241d3a0b36b232 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70126 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Rename 'internal_delay()' to 'default_delay()'Edward O'Callaghan2022-12-121-1/+1
| | | | | | | | | | | | | | | The non-custom driver programmer delay implementation 'internal_delay()' is unrelated specifically to the 'internal' programmer. The delay implementation is simply a platform-agnostic host delay implementation. Therefore, rename to simply default_delay(). Change-Id: I5e04adf16812ceb1480992c92bca25ed80f8897a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68855 Reviewed-by: Alexander Goncharov <chat@joursoir.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Move programmer_delay() out of programmer state machineEdward O'Callaghan2022-12-121-2/+2
| | | | | | | | | | | | | | | | | | | | Handle the special cases of both serprog and ch341a_spi. Also rewrite programmer_delay() to handle the two base cases of zero time and no valid flashctx yet before handling per master branching. Additionally, modify the custom delay function pointer signature to allow closure over the flashctx. This allows driver specific delay implementations to recover programmer specific opaque data within their delay implementations. Therefore programmer specific delay functions can avoid programmer specific globals. Change-Id: Id059abb58b31a066a408009073912da2b224d40c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tests: Add selfcheck to unit testsEvan Benn2022-12-051-0/+1
| | | | | | | | | | | | | | | | | Add unit tests for programmer_table, flashchips, and board_matches structs. The tests are derived from the selfcheck function, checking that the required fields have been filled in. BUG=b:140595239 BRANCH=None TEST=meson test Change-Id: I41cd014d9bf909296b6c28e3e00548e6883ff41a Signed-off-by: Evan Benn <evanbenn@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/69620 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Make probe_opcode() flashctx argument constNikolai Artemiev2022-12-041-2/+2
| | | | | | | | | | | | | | | | | | | Probing an opcode generally shouldn't involve mutating the flashctx state and currently no probe_opcode functions do that. Make the flashctx arg const so that call sites don't need to have a non-const pointer. BUG=b:253715389,b:253713774 BRANCH=none TEST=ninja test Change-Id: I19e98be50d682de2d2715417f8b7b8c62b871617 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70030 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* programmer: Drop dead fallback_map() boilerplateEdward O'Callaghan2022-11-121-2/+0
| | | | | | | | | | | | | | The fallback_{un}map() boilerplate code doesn't do anything, merely distracts away from otherwise linear control flow. Just drop it as anything in the future that could need such a thing is free to implement it when required. Change-Id: Ibb7760f807fae040416cef2797a7dbf6572f7df9 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68963 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.c: Move count_max_decode_exceeding() to cliEdward O'Callaghan2022-10-311-1/+0
| | | | | | | | | | | | The count_max_decode_exceeding() function is only ever called within the cli_classic logic so move it there and make it static. This further cleans up the flashrom.c symbol namespace. Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dirtyjtag: Add DirtyJTAG programmerJean THOMAS2022-10-151-0/+1
| | | | | | | | | | | | | | | | Add a new programmer driver for the DirtyJTAG project (a USB-JTAG firmware for STM32 MCUs). Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103 development board and a SST25VF020B SPI flash chip. Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913 Signed-off-by: Jean THOMAS <virgule@jeanthomas.me> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashrom.c: Remove custom mappers from opaque_masterJonathon Hall2022-10-081-2/+0
| | | | | | | | | | | | | No opaque masters have a custom mapper. The returned chipaddr is not fed back into the read/write/erase functions, so this would only be useful for side effects. Change-Id: I36f05154edda371b51f8ff416f019837ff1c243d Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68092 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers: Move (un)map_flash_region to par/spi/opaque_masterJonathon Hall2022-10-081-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Move (un)map_flash_region function pointers from programmer_entry to par_master, spi_master, and opaque_master. This enables programmers to specify a different mapper per bus, which is needed for the internal programmer. Mapping is closely tied to the way the memory is accessed using the other functions in the bus master structs. Validate that FWH/LPC programmers provide specialized mapping in register_par_master(); this is needed for chips with FEATURE_REGISTERMAP, which only exist on FWH or LPC buses. programmer.c: Update comment in fallback_map(), NULL return is the desired behavior. Test: Read firmware on SB600 Promontory mainboard (requires physmap) Test: Read firmware externally with ft2232_spi Test: Read firmware on ICH hwseq, verify physmap still occurs Change-Id: I9c3df6ae260bcdb246dfb0cd8e043919609b014b Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Co-Authored-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal.c: Pass `programmer_cfg` to `try_mtd()`Angel Pons2022-09-211-3/+6
| | | | | | | | | | | | | | | | | Programmer params are now passed via the `programmer_cfg` struct, but the internal programmer did not pass them to the `try_mtd()` function which was still using `NULL`. This problem resulted in a segmentation fault when trying to use the internal programmer. TEST=Make sure internal programmer does not segfault on Haswell ULT. Change-Id: I9e74bd68a1f9509a201dc518dbff96c27d68a3c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Retype variable `laptop_ok` with boolFelix Singer2022-09-081-1/+1
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `laptop_ok`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423 Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Retype variable `programmer_may_write` with boolFelix Singer2022-09-081-1/+1
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `programmer_may_write`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I69958527ae018a92f1c42734a7990d0c532dee0c Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: Retype appropriate variables with boolFelix Singer2022-09-081-2/+3
| | | | | | | | | | | | | Use the bool type instead of an integer for the variables `force_laptop`, `not_a_laptop`, `force_boardenable` and `force_boardmismatch` since this represents their purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I159d789112d7a778744b59b45133df3928b8445e Reviewed-on: https://review.coreboot.org/c/flashrom/+/66870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: plumb programmer_cfg into chipset_flash_enable()Edward O'Callaghan2022-09-071-1/+1
| | | | | | | | | Change-Id: I963c674d212ce791ee155020fa97bcf26cefca0c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Also plumb programmer_cfg though get_params. Change-Id: I480589bb50b47fdf5af259d068f49fedfce88ea5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* chipset_enable.c: Change doit() and enable_flash_\S() signaturesEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | | Ran; ``` $ sed -Ei 's/int enable_flash_(\S+)\(/int enable_flash_\1(const char *prog_param, /g' chipset_enable.c $ sed -Ei 's/return enable_flash_(\S+)\(/return enable_flash_\1(cfg, /g' chipset_enable.c ``` and dealt with special cases manually. Change-Id: I62c5d49a83ed4afb86ac3f0fae56defa1338ab4f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Fix drivers to pass programmer_cfg to pcidev_init()Edward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | Allow for programmer_cfg plumbing in pcidev.c The pci drivers impacted are plumbed here as well. Change-Id: Ie0c9d1c0866d44f64d037c596f2e30547fcfd58f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* sb600spi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Also plumb programmer_cfg though handle_imc and handle_speed. Change-Id: I82f9ee75df90c582ef345c00a5487c687f28cdd5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* it87spi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Allow passing programmer_cfg directly to programmerEdward O'Callaghan2022-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | Modify the type signature of each programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. ``` $ find -name '*.c' -exec sed -i 's/_init(void)/_init(const char *prog_param)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/get_params(/get_params(const char *prog_param, /g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param)/const struct programmer_cfg *cfg)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param,/const struct programmer_cfg *cfg,/g' '{}' \; ``` and manually fix up any remaining parts. Change-Id: I8bab51a635b9d3a43e1619a7a32b334f4ce2cdd2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Change signature of extract_programmer_param_str()Edward O'Callaghan2022-09-071-1/+2
| | | | | | | | | | | | | | | | | Results can be reproduced with the following invocation; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(/extract_programmer_param_str(NULL, /g' '{}' \; ``` This allows for a pointer to the actual programmer parameters to be passed instead of a global. Change-Id: I781a328fa280e0a9601050dd99a75af72c39c899 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* parallel.c: Consoldiate parallel master registration logicEdward O'Callaghan2022-08-251-9/+11
| | | | | | | | | | | | | | | | This is analogous to spi.c and opaque.c however parallel logic was previously never consoldiated. This free's up flashrom.c from namespace pollution. BUG=b:242246291 TEST=builds with both make and meson. Change-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Rename lspcon_i2c_spi to parade_lspconThomas Heijligen2022-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | The chip targeted by the `lspcon_i2c_spi` programmer is a Parade PS175. Rename the programmer to match the chips vendor / family instead of the generic LSPCON protocol. Remove the `_i2c_spi` ending in preparation to become an opaque master. The chip is visible on an Acer Chromebox CXI4. https://www.paradetech.com/products/ps175/ https://www.acer.com/ac/en/US/content/series/acerchromeboxcxi4 TEST: `make CONFIG_PARADE_LSPCON=yes` and `meson build -Dconfig_parade_lspcon=true` produces flashrom binaries with the parade_lspcon programmer included. Change-Id: I9148be6d9162c1722ff739929ca5e181b628dd57 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Add function to probe erase command opcode for all spi_masterAarya Chaumal2022-07-111-0/+2
| | | | | | | | | | | | | | | | | | | | Add a field, probe_opcode, to struct spi_master which points to a function returning a bool by checking if a given command is supported by the programmer in use. This is used for getting a whitelist of commands supported by the programmer, as some programmers like ichspi don't support all opcodes. Most programmers use the default function, which just returns true. ICHSPI and dummyflasher use their specialized function. Change-Id: I6852ef92788221f471a859c879f8aff42558d36d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it85spi: EOL supportEdward O'Callaghan2022-07-041-3/+0
| | | | | | | | | | | | | | | | | | | | | This code was originally introduced by ITE for now exceedingly old Chromebooks. The code has had very little attention to maintain it, unlikely tested for a long time and now seems to be just a technical burden to the flashrom project. If someone is later interested it could be resurrected for reference from git history. However, it needs quite a bit of work to bring it back into maintainable order. BUG=b:156143896,b:170689483 TEST=tree builds under meson+make and unit tests pass. Change-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-021-1/+1
| | | | | | | | | | | | | This patch changes the function name of extract_programmer_param() to extract_programmer_param_str() as this function name will clearly specify that it returns the value of the given parameter as a string. Signed-off-by: Chinmay Lonkar <chinmay20220@gmail.com> Change-Id: Id7b9fff4d3e1de22abd31b8123a1d237cd0f5c97 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* writeprotect.c: Allow opaque masters to hook {read,write}_register()Edward O'Callaghan2022-06-211-0/+8
| | | | | | | | | | | | | | | | | | | | Allow specialisation in opaque masters, such as ichspi hwseq, to write to status registers. Also update the dispatch logic in libflashrom to call wp code when status register access functions are provided by an opaque master. BUG=none BRANCH=none TEST=flashrom --wp-status on AMD and Intel DUTs Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Co-Authored-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64375 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-0/+516
Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 19:56:51 +0000