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* tree/: Rename ERROR_NONFATAL to ERROR_FLASHROM_NONFATALEdward O'Callaghan2022-11-091-1/+1
| | | | | | | | | | Change-Id: I5c30fec0cebab2b7d10e2789761889abc3a14dd3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Rename ERROR_FATAL to ERROR_FLASHROM_FATALEdward O'Callaghan2022-11-091-1/+1
| | | | | | | | Change-Id: I51ee789f9a1443bfff1e3c85c9b40b5023db6062 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.c: Make 'chip_to_probe' a param to probe_flash()Edward O'Callaghan2022-11-062-2/+2
| | | | | | | | | | | | | | | | | Apart from the very bespoke case of 'probe_w29ee011()' the override 'chip_to_probe' name is a nature parameter to 'probe_flash()'. However we can deal with w29ee011 by providing a probe specific validation function to check if the chip can indeed be overriden. TEST=`./flashrom -p internal --flash-name`. Change-Id: Ifcdace07ea2135d83dea92cfa5c6bec8d7ddf05d Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree/: Convert flashchip read func ptr to enumerateEdward O'Callaghan2022-11-011-1/+14
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I612d46fefedf2b69e7e2064aa857fa0756efb4e7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66788 Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip write func ptr to enumerateEdward O'Callaghan2022-11-011-1/+18
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I80149de169464b204fb09f1424a86fc645b740fd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree/: Convert flashchip probe func ptr to enumerateEdward O'Callaghan2022-11-011-1/+22
| | | | | | | | | | | | | | | | This forges the way for flashchips.c to be pure declarative data and lookup functions for dispatch to be pure. This means that the flashchips data could be extracted out to be agnostic data of the flashrom code and algorithms. TEST='R|W|E && --flash-name' on ARM, AMD & Intel DUT's. Change-Id: I00aaab9c83f305cd47e78c36d9c2867f2b73c396 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* flashrom.c: Move count_max_decode_exceeding() to cliEdward O'Callaghan2022-10-311-1/+0
| | | | | | | | | | | | The count_max_decode_exceeding() function is only ever called within the cli_classic logic so move it there and make it static. This further cleans up the flashrom.c symbol namespace. Change-Id: If050eab7db8560676c03d5005a2b391313a0d642 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree/: Convert flashchip decode range func ptr to enumNikolai Artemiev2022-10-281-3/+11
| | | | | | | | | | | | | | | | | | | | Replace the `decode_range` function pointer in `struct flashchip` to an enum value. The enum value can be used to find the corresponding function pointer by passing it to `lookup_decode_range_func_ptr()`. Removing function pointers like `decode_range` makes it possible to represent chip data in a declarative format that does not have to be stored as C source code. BUG=b:242479049 BRANCH=none TEST=ninja && ninja test Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6d08d414d3d1ddadc95ca1d407fc87c23ab543d Reviewed-on: https://review.coreboot.org/c/flashrom/+/67195 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flash.h: extend `struct tested` with .wp fieldSergii Dmytruk2022-10-232-9/+13
| | | | | | | | | | | | Using "B" letter for "block protection" in TEST_* macros. Ticket: https://ticket.coreboot.org/issues/377 Change-Id: I791400889159bc6f305fb05f3e2dd9a90dbe18a4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68179 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: provide flashrom context into programmer_delay()Alexander Goncharov2022-10-171-1/+2
| | | | | | | | | | | | | | | | | Modify the `programmer_delay` function signature to allow passing the flashrom context. Programmers that depend on internal delay should provide NULL as a context. The use of this function parameter will be introduced in CB:67393. TOPIC=programmer_handle_global TEST=builds Change-Id: Ibb0bce26ce2052853ee52158d7ba742967a9e229 Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* dirtyjtag: Add DirtyJTAG programmerJean THOMAS2022-10-151-0/+1
| | | | | | | | | | | | | | | | Add a new programmer driver for the DirtyJTAG project (a USB-JTAG firmware for STM32 MCUs). Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103 development board and a SST25VF020B SPI flash chip. Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913 Signed-off-by: Jean THOMAS <virgule@jeanthomas.me> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashrom.c: Remove custom mappers from opaque_masterJonathon Hall2022-10-081-2/+0
| | | | | | | | | | | | | No opaque masters have a custom mapper. The returned chipaddr is not fed back into the read/write/erase functions, so this would only be useful for side effects. Change-Id: I36f05154edda371b51f8ff416f019837ff1c243d Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/68092 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers: Move (un)map_flash_region to par/spi/opaque_masterJonathon Hall2022-10-082-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Move (un)map_flash_region function pointers from programmer_entry to par_master, spi_master, and opaque_master. This enables programmers to specify a different mapper per bus, which is needed for the internal programmer. Mapping is closely tied to the way the memory is accessed using the other functions in the bus master structs. Validate that FWH/LPC programmers provide specialized mapping in register_par_master(); this is needed for chips with FEATURE_REGISTERMAP, which only exist on FWH or LPC buses. programmer.c: Update comment in fallback_map(), NULL return is the desired behavior. Test: Read firmware on SB600 Promontory mainboard (requires physmap) Test: Read firmware externally with ft2232_spi Test: Read firmware on ICH hwseq, verify physmap still occurs Change-Id: I9c3df6ae260bcdb246dfb0cd8e043919609b014b Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Co-Authored-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* internal.c: Pass `programmer_cfg` to `try_mtd()`Angel Pons2022-09-211-3/+6
| | | | | | | | | | | | | | | | | Programmer params are now passed via the `programmer_cfg` struct, but the internal programmer did not pass them to the `try_mtd()` function which was still using `NULL`. This problem resulted in a segmentation fault when trying to use the internal programmer. TEST=Make sure internal programmer does not segfault on Haswell ULT. Change-Id: I9e74bd68a1f9509a201dc518dbff96c27d68a3c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Retype variable `laptop_ok` with boolFelix Singer2022-09-081-1/+1
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `laptop_ok`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I5d9fc3516bc2d29f11b056e35b3e5e324ce93423 Reviewed-on: https://review.coreboot.org/c/flashrom/+/66891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Retype variable `programmer_may_write` with boolFelix Singer2022-09-081-1/+1
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `programmer_may_write`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I69958527ae018a92f1c42734a7990d0c532dee0c Reviewed-on: https://review.coreboot.org/c/flashrom/+/66885 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* internal.c: Retype appropriate variables with boolFelix Singer2022-09-081-2/+3
| | | | | | | | | | | | | Use the bool type instead of an integer for the variables `force_laptop`, `not_a_laptop`, `force_boardenable` and `force_boardmismatch` since this represents their purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I159d789112d7a778744b59b45133df3928b8445e Reviewed-on: https://review.coreboot.org/c/flashrom/+/66870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: plumb programmer_cfg into chipset_flash_enable()Edward O'Callaghan2022-09-071-1/+1
| | | | | | | | | Change-Id: I963c674d212ce791ee155020fa97bcf26cefca0c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* ichspi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Also plumb programmer_cfg though get_params. Change-Id: I480589bb50b47fdf5af259d068f49fedfce88ea5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* chipset_enable.c: Change doit() and enable_flash_\S() signaturesEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | | Ran; ``` $ sed -Ei 's/int enable_flash_(\S+)\(/int enable_flash_\1(const char *prog_param, /g' chipset_enable.c $ sed -Ei 's/return enable_flash_(\S+)\(/return enable_flash_\1(cfg, /g' chipset_enable.c ``` and dealt with special cases manually. Change-Id: I62c5d49a83ed4afb86ac3f0fae56defa1338ab4f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Fix drivers to pass programmer_cfg to pcidev_init()Edward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | Allow for programmer_cfg plumbing in pcidev.c The pci drivers impacted are plumbed here as well. Change-Id: Ie0c9d1c0866d44f64d037c596f2e30547fcfd58f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* usb_device.c: Allow for programmer_cfg plumbingEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | The only driver impacted is raiden_debug_spi.c and so plumb state directly. Change-Id: I85ff3117de8743b0a548dad98875cc41f48cac93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Port programmers to pass programmer_cfg to extractorsEdward O'Callaghan2022-09-071-1/+3
| | | | | | | | | | | | | | | | | | | | | Ran; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(NULL/extract_programmer_param_str(cfg/g' '{}' \; ``` Manually fix i2c_helper_linux.c and other cases after. Treat cases of; - pcidev.c , and - usb_device.c as exceptional to be dealt with in later patches. Change-Id: If7b7987e803d35582dda219652a6fc3ed5729b47 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* sb600spi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Also plumb programmer_cfg though handle_imc and handle_speed. Change-Id: I82f9ee75df90c582ef345c00a5487c687f28cdd5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* it87spi.c: Allow passing programmer_cfg directlyEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | Modify the type signature of the programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. Change-Id: I598b1811c9734f41eee205d5a2b51ad8ac79e3ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* tree: Allow passing programmer_cfg directly to programmerEdward O'Callaghan2022-09-071-2/+2
| | | | | | | | | | | | | | | | | | | | | Modify the type signature of each programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. ``` $ find -name '*.c' -exec sed -i 's/_init(void)/_init(const char *prog_param)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/get_params(/get_params(const char *prog_param, /g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param)/const struct programmer_cfg *cfg)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param,/const struct programmer_cfg *cfg,/g' '{}' \; ``` and manually fix up any remaining parts. Change-Id: I8bab51a635b9d3a43e1619a7a32b334f4ce2cdd2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Change signature of extract_programmer_param_str()Edward O'Callaghan2022-09-071-1/+2
| | | | | | | | | | | | | | | | | Results can be reproduced with the following invocation; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(/extract_programmer_param_str(NULL, /g' '{}' \; ``` This allows for a pointer to the actual programmer parameters to be passed instead of a global. Change-Id: I781a328fa280e0a9601050dd99a75af72c39c899 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* parallel.c: Consoldiate parallel master registration logicEdward O'Callaghan2022-08-252-9/+12
| | | | | | | | | | | | | | | | This is analogous to spi.c and opaque.c however parallel logic was previously never consoldiated. This free's up flashrom.c from namespace pollution. BUG=b:242246291 TEST=builds with both make and meson. Change-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Move write_buf_to_include_args() to cli_classic.cEdward O'Callaghan2022-08-251-1/+0
| | | | | | | | | | | | | | | | | The write_buf_to_include_args() helper is only ever used by the cli frontend therefore make it static local to the user. BUG=b:242246291 TEST=builds Change-Id: Ia16bf4b8e46a011aa45f98089d43904b077833a0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: Move read_buf_from_include_args() into cli_classic.cEdward O'Callaghan2022-08-251-1/+0
| | | | | | | | | | | | | | | | | The read_buf_from_include_args() helper is only ever used by the cli frontend therefore make it static local to the user. BUG=b:242246291 TEST=builds Change-Id: I9dee63d67320085e16c64eefb2723169f49f07aa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: flatten out write_buf_to_include_args()Edward O'Callaghan2022-08-251-1/+1
| | | | | | | | | | | | | | | | | | | write_buf_to_include_args() does not need the whole flashctx, rather it works with a fix layout and buffer. Just pass what state is actually required. BUG=b:242246291 TEST=builds Change-Id: I885c4395356eef27746c66300233f07f4718ccdf Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66644 Reviewed-by: Evan Benn <evanbenn@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashrom.c: flatten out read_buf_from_include_args()Edward O'Callaghan2022-08-251-1/+1
| | | | | | | | | | | | | | | | | | | read_buf_from_include_args() does not need the whole flashctx, rather it works with a fix layout and buffer. Just pass what state is actually required. BUG=b:242246291 TEST=builds Change-Id: Ieadd68895c7ba05cc3d770d304351b02622f14d7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66633 Reviewed-by: Evan Benn <evanbenn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Thomas Heijligen <src@posteo.de>
* include/ich_descriptors.h: Add missing includeEdward O'Callaghan2022-08-081-0/+1
| | | | | | | | | | | | | Avoid transitively including the bool type for the ich_descriptor functionality. Change-Id: I2d9eb833ca9198c0586543d3f0074893aac5c6fb Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matei Dibu <matdibu@protonmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Rename lspcon_i2c_spi to parade_lspconThomas Heijligen2022-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | The chip targeted by the `lspcon_i2c_spi` programmer is a Parade PS175. Rename the programmer to match the chips vendor / family instead of the generic LSPCON protocol. Remove the `_i2c_spi` ending in preparation to become an opaque master. The chip is visible on an Acer Chromebox CXI4. https://www.paradetech.com/products/ps175/ https://www.acer.com/ac/en/US/content/series/acerchromeboxcxi4 TEST: `make CONFIG_PARADE_LSPCON=yes` and `meson build -Dconfig_parade_lspcon=true` produces flashrom binaries with the parade_lspcon programmer included. Change-Id: I9148be6d9162c1722ff739929ca5e181b628dd57 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Add function to probe erase command opcode for all spi_masterAarya Chaumal2022-07-111-0/+2
| | | | | | | | | | | | | | | | | | | | Add a field, probe_opcode, to struct spi_master which points to a function returning a bool by checking if a given command is supported by the programmer in use. This is used for getting a whitelist of commands supported by the programmer, as some programmers like ichspi don't support all opcodes. Most programmers use the default function, which just returns true. ICHSPI and dummyflasher use their specialized function. Change-Id: I6852ef92788221f471a859c879f8aff42558d36d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* it85spi: EOL supportEdward O'Callaghan2022-07-041-3/+0
| | | | | | | | | | | | | | | | | | | | | This code was originally introduced by ITE for now exceedingly old Chromebooks. The code has had very little attention to maintain it, unlikely tested for a long time and now seems to be just a technical burden to the flashrom project. If someone is later interested it could be resurrected for reference from git history. However, it needs quite a bit of work to bring it back into maintainable order. BUG=b:156143896,b:170689483 TEST=tree builds under meson+make and unit tests pass. Change-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-022-2/+2
| | | | | | | | | | | | | This patch changes the function name of extract_programmer_param() to extract_programmer_param_str() as this function name will clearly specify that it returns the value of the given parameter as a string. Signed-off-by: Chinmay Lonkar <chinmay20220@gmail.com> Change-Id: Id7b9fff4d3e1de22abd31b8123a1d237cd0f5c97 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi25.c: Add function to return opcode of passed erase fucntion pointerAarya Chaumal2022-06-271-0/+1
| | | | | | | | | | | | | There is a function, spi_get_erasefn_from_opcode, which returns the erase function for given opcode. Add a function which does the opposite i.e. returns the opcode for given erase function. Change-Id: Ia3aefc9b9465efdd16b1678bb2ada9a23f00d316 Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716Nico Huber2022-06-232-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8Nico Huber2022-06-221-5/+6
| | | | | | | | | | | | | | There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* writeprotect.c: Allow opaque masters to hook {read,write}_register()Edward O'Callaghan2022-06-212-0/+11
| | | | | | | | | | | | | | | | | | | | Allow specialisation in opaque masters, such as ichspi hwseq, to write to status registers. Also update the dispatch logic in libflashrom to call wp code when status register access functions are provided by an opaque master. BUG=none BRANCH=none TEST=flashrom --wp-status on AMD and Intel DUTs Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Co-Authored-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64375 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add Spansion (today Infineon) S25FL128L and S25FL256LNico Huber2022-06-202-0/+3
| | | | | | | | | | | | | | | | | | | | | | | These chips seem to be rather regular, supporting 2.7V..3.6V, the common erase block sizes 4KiB, 32KiB, 64KiB and the usual block- protection bits. Status/configuration register naming differs from other vendors, though. These chips have 2 status registers plus 3 configuration registers. Configuration registers 1 & 2 match status registers 2 & 3 of what we are used from other vendors. Read opcodes match too, however writes are always done through the WRSR instruction which can write up to 4 bytes (SR1, CR1, CR2, CR3). S25FL256L supports native 4BA commands and entering a 4BA mode. However, it uses an unusual opcode (0x53) for the 32KiB 4BA block erase. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747 Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25_statusreg: Allow WRSR_EXT for Status Register 3Nico Huber2022-06-202-2/+3
| | | | | | | | | | | | | | | | | Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to write more than 2 registers. So align SR2 and SR3 support: The current FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3 is added. Also, WRSR3 needs a separate flag now. Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094 Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de>
* dummyflasher: Wire variable size feature via opaque infraAnastasia Klimchuk2022-06-161-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire "variable size" feature in dummy programmer via opaque infra. This patch fixes the broken build with CONFIG_DUMMY=no. Dummyflasher registers opaque master for the case when it is initialised with EMULATE_VARIABLE_SIZE. Dummy opaque master emulates read/write/erase as simple memory operations over `data->flashchip_contents`. The feature works via "Opaque flash chip" in flashchips.c which has one block eraser at the moment. If this changes in future, each block eraser needs to be updated in `probe_variable_size`. Fixes: https://ticket.coreboot.org/issues/365 TEST=the following scenarious run successfully Testing build $ make clean && make CONFIG_DUMMY=no $ flashrom -h : dummy is not in the list $ make clean && make CONFIG_EVERYTHING=yes $ flashrom -h : dummy is in the list Testing "variable size" feature $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V $ head -c 8388608 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V also same as above with erase_to_zero=yes Testing standard flow $ flashrom -p dummy:emulate=W25Q128FV -V $ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V $ head -c 16777216 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V Testing invalid combination of programmer params (`init_data` fails and prints error message which is WAI) $ flashrom -p dummy:size=8388608 -V -> init_data: size parameter is only valid for VARIABLE_SIZE chip. $ flashrom -p dummy:emulate=VARIABLE_SIZE -V -> init_data: the size parameter is not given. $ flashrom -p dummy:emulate=W25Q128FV,erase_to_zero=yes -V -> init_data: erase_to_zero parameter is not valid for real chip. Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Consolidate BIT() macroEdward O'Callaghan2022-06-101-0/+2
| | | | | | | | | Change-Id: I7e61f7671b70ca5ed751d99405714436bcd18d5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Add W25Q512NW-IM ID to flashromAtul Dhudase2022-06-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Winbond W25Q512NW-IM chip ID and specs to flashrom. BUG=b:200173901 BRANCH=none TEST=flash W25Q512NW-IM using CCD. Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890 Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shelley Chen <shchen@chromium.org> Original-Commit-Queue: Shelley Chen <shchen@chromium.org> (cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61) Note: this commit was cherry-picked from the cros tree but includes corrections to errors in the original commit's 4BA feature flags that were spotted by Angel Pons Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* libflashrom: Return progress state to the library userRichard Hughes2022-05-252-1/+33
| | | | | | | | | | | | | | | | | | | | | | Projects using libflashrom like fwupd expect the user to wait for the operation to complete. To avoid the user thinking the process has "hung" or "got stuck" report back the progress complete of the erase, write and read operations. Add a new --progress flag to the CLI to report progress of operations. Include a test for the dummy spi25 device. TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c Signed-off-by: Richard Hughes <richard@hughsie.com> Signed-off-by: Daniel Campello <campello@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* include/flash.h: Drop dead struct membersEdward O'Callaghan2022-05-171-2/+0
| | | | | | | | | | | | | These were part of the original wp implementation, now dead code left over. Change-Id: I43b25175c6ff833b822a93c4e752a28cf97d64b8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom.c: Make need_erase() helper static localEdward O'Callaghan2022-05-171-1/+0
| | | | | | | | | | | | The need_erase() helper is only used within flashrom.c Change-Id: Ic0946bb109fca2fc18e15eefa11cccea284ded0b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/64369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashrom: Drop read_flash_to_file() usageEdward O'Callaghan2022-05-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspire towards a goal of making cli_classic more of just a user of libflashrom than having quasi-parallel paths in flashrom.c This converts remaining read_flash_to_file() usage to the do_read() provider wrapper around libflashrom. BUG=b:208132085 TEST=` sudo ./flashrom -p ft2232_spi:type=232H,divisor=1000 -f -r out -c W25X05 Flashrom output: No EEPROM/flash device found. Force read (-f -r -c) requested, pretending the chip is there: Assuming Winbond flash chip "W25X05" (64 kB, SPI) on ft2232_spi. Please note that forced reads most likely contain garbage. Block protection could not be disabled! Reading flash... done. Data read: xxd out-1khz 00000000: 0000 07ff ffff e000 0000 7fff fffe 0000 ................ 00000010: 0007 ffff ffe0 0000 007f ffff fe00 0000 ................ 00000020: 07ff ffff e000 0000 7fff fffe 0000 0007 ................ 00000030: ffff ffe0 0000 007f ffff fe00 0000 0fff ................ xxd out-100khz 00000000: b6db 6db6 db6d b6db 6db6 db6d b6db 6db6 ..m..m..m..m..m. 00000010: db6d b6db 6db6 db6d b6db 6db6 db6d b6db .m..m..m..m..m.. 00000020: 6db6 db6d b6db 6db6 db24 9249 2492 4924 m..m..m..$.I$.I$ 00000030: 9249 2492 4924 9249 2492 4924 9249 2492 .I$.I$.I$.I$.I$. ` Change-Id: I4b690b688acf9d5deb46e8642a252a2132ea8c73 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Tested-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 19:54:05 +0000