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* spi25: Debug flashrom crash when Write Protect is ONYuji Sasaki2020-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hardware write protect is applied, flashrom crashed and generate coredump. spi_disable_blockprotect_generic() calls flash->chip->printlock() method when disable was failed, but this method is optional, can be NULL depends on type of flashrom chip. NULL pointer check before call is added to avoid crash. BRANCH=none BUG=b:129083894 TEST=Run on Mistral P2 (On CR50 console, run "wp disable") flashrom --wp-range 0 0x400000 flashrom --wp-enable (On CR50 console, run "wp enable") flashrom -r /tmp/test.bin Verify "Block protection could not be disabled!" is shown, but flash read completes. Signed-off-by: Yuji Sasaki <sasakiy@chromium.org> Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e Reviewed-on: https://chromium-review.googlesource.com/1535140 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-011-86/+0
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-3/+3
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: port S25FS(128S) chip from chromiumossibradzic2020-04-221-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine which type of reset feature is enabled at the time (legacy or S25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or set programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do the actual testing, S25FS128S (Small Sectors), which I had fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. Full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Most of the ported functions are originally from s25f.c found at https://chromium.googlesource.com/chromiumos/third_party/flashrom with exception of spi_restore_status which is defined in spi25_statusreg.c. The rest of macros and OP codes are defined in same files as in this commit. Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Remove unused functions with no prototypesJacob Garber2019-06-231-14/+0
| | | | | | | | | | | | | | | | | These functions are no longer used, or were never used in the first place. generate_testpattern() - Introduced in commit eaac68bf8b, never used list_programmers() - Introduced in commit 552420b0d6, never used pci_dev_find_filter() - Prototype removed in commit 5c316f9549 erase_chip_jedec() - Usage and prototype removed in commit f52f784bb3 printlock_regspace2_blocks() - Introduced in commit ef3ac8ac17, never used spi_write_status_enable() - Usage dropped in commit fcbdbbc0d4 Change-Id: I742164670521fea65ffa3808446594848ce63cec Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix several -Wno-implicit-fallthrough warningsRichard Hughes2019-02-111-1/+4
| | | | | | | | | | | | GCC is picky about the comment being where the break should go. Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6 Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/30406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)Wei Hu2018-05-061-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch seems to have originally been from https://patchwork.coreboot.org/patch/4126/ . The most recent version seems to be in OpenEmbedded (commit 503a572) which added support for 16Mbit and 32Mbit variants. The OpenEmbedded patch also makes changes to linux_spi.c to add some debug prints which are omitted in this version. From the original commit message: Differences between SST26 and SST25: 1. The WREN instruction must be executed prior to WRSR [Section 5.31]. There is no EWSR. 2. Block protection bits are no longer in the status register. There is a dedicated 144-bit register [Table 5-6]. The device is write-protected by default. A Global Block-Protection Unlock command unlocks the entire memory [Section 4.1]. Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219 Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Reviewed-on: https://review.coreboot.org/25962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25_statusreg: Return defined value on failed RDSRNico Huber2017-11-051-1/+4
| | | | | | | | | | | The interface of spi_read_status_register() is broken and can't return errors. Let's not return random stack data at least. Change-Id: I714b20001a5443bba665c2e0061ca14069777581 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add support for SST SST25WF020A, SST25WF040B, SST25WF080BBen Gardner2015-11-221-0/+13
| | | | | | | | | | | | | | | | Apart from the strange ID (using Sanyo's vendor ID 0x62) the main difference from the plain SST25WF series is that they lack op codes 0xAD (AAI Word program) and 0x52 (32K erase). The smallest version does not support dual I/O operations either. SST25WF080B was tested under Linux with spidev. Corresponding to flashrom svn r1901. Tested-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 22Stefan Tauner2015-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - AOpen UK79G-1394 (used in EZ18 barebones) Reported by Lawrence Gough - ASUS M4N78 SE Reported by Dima Veselov - ASUS P5LD2-VM Mark board enable as tested (reported by Dima Veselov) - GIGABYTE GA-970A-UD3P (rev. 2.0) Reported by trucmar on IRC - GIGABYTE GA-990FXA-UD3 (rev. 4.0) Reported by ROKO__ on IRC - GIGABYTE GA-H77-DS3H (rev. 1.1) Reported by Evgeniy Edigarev - GIGABYTE GA-P55-USB3 (rev. 2.0) Reported by Måns Thörnqvist - MSI MS-7817 (H81M-E33) Reported by Igor Kolker Chipsets: - Marked Intel Bay Trail (0x0f1c) as tested OK Reported by Antonio Ospite - Refine Intel IDs * Add IDs for Braswell * Add IDs for 9 Series PCHs (e.g. H97, Z97) * Rename Wellsburg devices slightly Flash chips: - Atmel AT25DF041A to PREW (+PREW) Reported by Tai-hwa Liang - Atmel AT26DF161 to PREW (+EW) Reported by Steve Shenton - Atmel AT45DB011D to PREW (+PREW) Reported by The Raven - Atmel AT45DB642D to PREW (+PREW) Reported by Mahesh Mokal - Eon EN25F32 to PREW (+PREW) Reported by Arman Khodabande - Eon EN25F40 to PREW (+REW) Reported by Jerrad Pierce - Eon EN25QH16 to PREW (+EW) Reported by Ben Johnson - GigaDevice GD25Q20(B) to PREW (+PREW) Reported by Gilles Aurejac - Macronix MX25U6435E/F to PR (+PR) Reported by Matt Taggart - PMC Pm25LV512(A) to PREW (+PREW) Reported by The Raven - SST SST39VF020 to PREW (+PREW) Reported by Urja Rannikko - Winbond W25Q40.V to PREW (+EW) Reported by Torben Nielsen - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E). - Add MX25L6465E variant. - There was never a MX25L12805 AFAICT. - Split MX25L12805 from models with the same ID but an additional 32 kB eraser: MX25L12835F/MX25L12845E/MX25L12865E. - Add a bunch of ST parallel NOR flash chip IDs. Miscellaneous: - Whitelist ThinkPad X200. - Constify master parameter of register_master(). - Remove FEATURE_BYTEWRITES because it was never used at all. - Refine hwseq messages and make them less prominent. - Fix the yet unused PRIxCHIPADDR format string thingy. - Fix copy&paste error in spi_prettyprint_status_register_bp(). Spotted by Pablo Cases. - Add an additional SMBus controller revision to identify another Yangtze model. Thanks to Dan Christensen for reporting this issue. - dediprog: add missing include for stdlib.h. This fixes (at least) building on FreeBSD and DragonflyBSD with gcc. - Remove references to struct pci_filter from programmer.h. It is only needed in internal.c where it has a complete type. Having it in programmer.h provokes a warning by some old versions of gcc. - Tiny other stuff. Corresponding to flashrom svn r1879. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Sanyo LE25FW106Stefan Tauner2014-06-041-0/+7
| | | | | | | | | | | Also, add spi_disable_blockprotect_bp1_srwd(). Originally written and tested by The Raven <originalraven@hotmail.com>. Corresponding to flashrom svn r1818. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Rename some spi_prettyprint_status_register_* functionsStefan Tauner2014-05-271-6/+6
| | | | | | | | | | | | Spi_prettyprint_status_register_default_bpX -> spi_prettyprint_status_register_bpX_srwd Why was the default in there anyway? :) Corresponding to flashrom svn r1802. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for ESMT F25L32PAStefan Tauner2014-05-271-0/+13
| | | | | | | Corresponding to flashrom svn r1801. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 20Stefan Tauner2014-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - abit BX6 2.0 Reported by Stefan Tauner - Acer EM61SM/EM61PM (used in Acer Aspire T180) Reported by Benjamin Bellec - ADLINK Express-HR Reported by Obermair Thomas - ASUS M3N-H/HDMI Reported by Franc Serres - Attro G5G100-P Reported by Christoph Grenz - ASRock 960GM-GS3 FX Reported by Fuley Istvan - Elitegroup P6BAP-A+ (V2.2) Reported by Arnaldo Pirrone - Elitegroup GeForce7050M-M (V2.0) Reported by Leif Middelschulte - Fujitsu D3041-A1 (used in ESPRIMO P2560) Reported by Daggi Duck - GIGABYTE GA-8S648 Reported by TeslaBIOS - GIGABYTE GA-970A-D3P (rev. 1.0) Reported by Jean-Francois Pirus - GIGABYTE GA-B85M-D3H Reported by Mladen Milinković - GIGABYTE GA-X79-UD3 Reported by Jeff O'Neil - GIGABYTE GA-X79-UP4 (rev. 1.0) Reported by George Spelvin - GIGABYTE GA-Z68MA-D2H-B3 (rev. 1.3) Reported by Vangelis Skarmoutsos - GIGABYTE GA-Z87-HD3 Reported by virii5 - Lenovo Tilapia CRB Reported by jenkins56 on IRC - MSI GT60-2OD (notebook, only with layout patches) Reported by Vasiliy Vylegzhanin - MSI MS-6704 (845PE Max2 PCB 1.0) (Pure Version w/o raid) Reported by professorll - MSI MS-7399 1.1 (used in Acer Aspire M5640/M3640) Reported by Koen Rousseau - MSI MS-7125 (K8N Neo4(-F/FI/FX)) We had a board enable for that one for years, but it was not (and still is not) completely clear which boards are covered. - MSI MS-7522 (MSI X58 Pro-E) Reported by Gianluigi Tiesi - PCWARE APM80-D3 Reported by César Augusto Jakoby - Pegatron IPP7A-CP Reported by Илья Шипко - Supermicro H8QME-2 Reported by Greg Tippitt - Supermicro X7SPA-H Reported by Kyle Bentley - Supermicro X7SPE-HF-D525 Reported by Micah Anderson - Supermicro X8DTE Reported by Mark Nipper - Supermicro X8SIL-F Reported by Peter Samuelson - ZOTAC IONITX-A (-E) version Reported by Maciej Wroniecki NOT OK: - Supermicro X10SLM-F Reported by Micah Anderson Flash chips: - Atmel AT29C020 to PREW (+PREW) It was marked like that in the past, but I could not find the reason why the test bits were reset. Urja Rannikko tested it again and it still works. - Eon EN25F10 to PREW (+PREW) Reported by Stolmár Tamás - Eon EN25QH64 to PR (+PR) Reported by Vladimir 'φ-coder' Serbinenko - GigaDevice GD25Q32(B) to PREW (+PREW) Reported by mrnuke - Macronix MX25L512(E)/MX25V512(C) to PREW (+PREW) Reported by Jamie Nichol - Macronix MX25L2005(C) to PREW (+PREW) Reported by Давыдов Дмитрий - Micron/Numonyx/ST N25Q064..1E to PREW (+PREW) Reported by Paolo Zambotti - Pmc Pm25LD010(C) to PREW (+PREW) Reported by Vasile Ceteras - Micron/Numonyx/ST M25P16 to PREW (+EW) Reported by raven - Micron/Numonyx/ST M25PX64 to PREW (+W) Reported by Zaolin - SST SST25VF020B to PREW (+PREW) Reported by Michaël Zweers - SST SST49LF040 to PREW (+W) Reported by Oskar Enoksson - Add support for MX25L3273E (evil twin of MX25L3205 et al.) Also, add MX25L1673 and MX25L6473E to the names of their twins and add a note about MX25L8073E. - Winbond W25X32 to PREW (+REW) Reported by The Raven - Winbond W29C010 etc. to PREW (+W) Reported by san Chipsets tested OK: - Intel NM70 (8086:1e5f) Reported by mrnuke - Intel C204 (8086:1c54) Reported by Vasiliy Vylegzhanin - Intel QM67 (8086:1c4f) Reported by Obermair Thomas - Intel HM77 (8086:1e57) Reported by Vasiliy Vylegzhanin - Intel B85 (8086:8c50) Reported by Mladen Milinković - Intel HM87 (8086:8c4b) Reported by Vasiliy Vylegzhanin - Intel Z87 (8086:8c44) Reported by virii5 - NVIDIA MCP51 (10de:0261) Reported by Marcin Kościelnicki - SiS 648 (1039:0648) Reported by TeslaBIOS Miscellaneous: - Mark ARM-USB-TINY-H as tested in ft2232_spi (reported by _nanodev_). - getrevision.sh: Ignore failing date calls. - getrevision.sh: Fix -u and -l for older git versions which require = for the git log grep parameter. - Corrected K8T Neo2-F entries due to a report from Stelios Tsampas. - Add "-p internal" to output that requests users to send flashrom -V logs. - Add Macbook2,1, Thinkpad X230, EasyNote LM85 to laptop whitelist. - Tiny other stuff. Corresponding to flashrom svn r1783. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Atmel AT45DB* chipsAidan Thornton2013-08-271-1/+1
| | | | | | | | Corresponding to flashrom svn r1723. Signed-off-by: Aidan Thornton <makosoft@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 18Stefan Tauner2013-07-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS C60M1-I http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html - ASUS P8H77-I http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - ASUS P8H77-M http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html - ASUS P8P67 LE (B2) http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html - Elitegroup GeForce6100PM-M2 (V3.0) http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html - GIGABYTE GA-P55A-UD7 http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html - MSI B75MA-E33 (MS-7808) http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - MSI H77MA-G43 (MS-7756) http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html - MSI KA780G (MS-7551) http://paste.flashrom.org/view.php?id=1617 - SAPPHIRE IPC-E350M1 Reported by xvilka on IRC - Supermicro X8DTG-D http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html NOT OK: - ASRock Fatal1ty Z77 Performance http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html - ASRock Z68 Extreme4 http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html - ASUS P8B75-M LE http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html - ASUS P8P67-M PRO http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html - ASUS P8Z68-V LE http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html - Intel DQ77MK http://paste.flashrom.org/view.php?id=1603 - Supermicro X9DRD-7LN4F http://paste.flashrom.org/view.php?id=1582 - Supermicro X9SCE-F http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html - Supermicro X9SCM-F http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html - Tyan S7066 http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html Chipsets: - Marked Intel B75 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - Marked Intel H77 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - Removed 10de:03e2 because it is apparently the MCP61 host bridge. It was reclassified to Host Bridge in the PCI device ID database and there is at least one report suggesting this configuration too: http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html - Added MCP89 which hopefully works with the code for previous versions. Thanks to James Laird for submitting this change. Tested flash chips: - Atmel AT25DF641(A) to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html - Atmel AT25F512 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html Also, change its ID according to Modification of PCN SC040401A: "There has been a change in the returned value of the Product Identification (RDID) command, the AT25F512A RDID code is 65h compared to 60h from the AT25F512 product." It seems to be quite likely that all AT25F512 are fully functional relabeled AT25F1024 chips. There are even some hints in the datasheet: in table 6 they stress that address pin 16 needs to be low under all circum- stances; while continuous reads can wrap around on the AT25F1024 the DS notes "For the AT25F512, the read command must be terminated when the highest address (00FFFF) is reached." OTOH the lock bit semantics are different, but this has not been tested thoroughly - Atmel AT25F512A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1569 - Eon EN25F05 to PREW (+PREW) http://paste.flashrom.org/view.php?id=1571 - Macronix MX25L12805(D) to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P) Tested by Stefan Tauner - Micron/Numonyx/ST M25PX80 to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P) Tested by Stefan Tauner - SST SST25VF040B to PREW (+PREW) http://paste.flashrom.org/view.php?id=1574 - SST SST25VF040B.REMS to PREW (+EW) http://paste.flashrom.org/view.php?id=1575 - ST M25P05-A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1576 - ST M29W512B to PREW (+W) http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html - Winbond W25Q64.W to PREW (+PREW) Tested by the chromiumos guys. - Winbond W25Q128.V to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html - Winbond W25X20 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html Miscellaneous: - Add Lenovo X201 to the laptop whitelist. - Add chip IDs for the ESMT F25L..QA family. - Add chip IDs for a few Macronix MX25 models. - The list of flashchips is not sorted strictly alphabetically and should not be either. Refine the comment explaining the scheme on top of the list. - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb). - Use z length modifier in (more) prints for size_t types. - Remove chips >16MB again because our current implementation of memory mapping the flash chip violates common rules by mapping a window as large as the chip. This leads to failing mmaps as can be seen here: http://paste.flashrom.org/view.php?id=1695 - Document spispeed parameter of linux_spi (and fix some leaks). - Rephrase the "multiple chips detected" message because it was confusing. - Skip verification step if the image is equal to the flash contents. - Tiny other stuff. Corresponding to flashrom svn r1702. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for remaining Numonyx (Micron) N25Q chipsNikolay Nikolaev2013-06-281-0/+22
| | | | | | | | | | | | | | | | | | | | Add... - N25Q128..3E - N25Q128..1E - N25Q256..1E (defunct due to addressing) - N25Q256..3E (defunct due to addressing) - N25Q512..1E (defunct due to addressing) - N25Q512..3E (defunct due to addressing) - N25Q00A..3G (defunct due to addressing) Also, refine existing family members. Corresponding to flashrom svn r1693. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Spansion S25FL...S chipsNikolay Nikolaev2013-06-281-3/+5
| | | | | | | | | | | | | | | Add... - S25FL128S - S25FL256S uniform version (defunct due to addressing) - S25FL512S uniform version (defunct due to addressing) Merge Intel S33 status register functions with this one's. Corresponding to flashrom svn r1692. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Eon EN25S seriesNikolay Nikolaev2013-06-281-0/+14
| | | | | | | | | | | | | | | | | | Add... - EN25S10 - EN25S20 - EN25S40 - EN25S80 - EN25S16 - EN25S32 - EN25S64 Corresponding to flashrom svn r1687. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Nantronics N25 seriesStefan Tauner2013-06-281-2/+2
| | | | | | | | | | | | | | Add... - N25S10 - N25S20 - N25S40 - N25S80 - N25S16 Corresponding to flashrom svn r1683. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Introduce additional SPI status register helpersStefan Tauner2013-06-281-6/+43
| | | | | | | | | | | | | | | | | | - spi_prettyprint_status_register_default_welwip(): It just prettyprints the plain hex value and the welwip bits. - spi_prettyprint_status_register_default_bp4(): Prints the hex value, welwip, bp0-5 and srwd bits. - spi_disable_blockprotect_bp2_srwd(), - spi_disable_blockprotect_bp3_srwd() and spi_disable_blockprotect_bp4_srwd(): Three new common block unprotection functions for the frequent cases where there is a status register lock bit at bit #7 and some block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively. Corresponding to flashrom svn r1681. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Fix unlocking function for most Atmel AT2[56]D* chipsStefan Tauner2013-06-201-20/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | I broke unlocking them correctly in r1635 while refactoring (NB: the commit log including the overly selfconfident statement about the "bug in spi_disable_blockprotect_at25df()"). Affected chips have per sector protection bits and the write protection bits in the status register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all sectors at once but in a way that was not anticipated when refactoring the spi25 unlocking functions into spi_disable_blockprotect_generic(). To globally unprotect not only the protection bits (2 and 3) have 0 to be written to them but also bits 4 and 5 which normally would not be touched by spi_disable_blockprotect_generic(). Some of the chips also support a permanent lockdown with fuses which we do not handle yet. To fix this without copying the whole method I introduce another mask parameter to spi_disable_blockprotect_generic() namely unprotect_mask. See verbose comments inline for details. Also, prettyprint the status register after trying to disable the block protection fails. Corresponding to flashrom svn r1679. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Chi Zhang <zhangchi866@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for PMC Pm25LD seriesStefan Tauner2013-04-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for - Pm25LD256C - Pm25LD512(C) - Pm25LD010(C) - Pm25LD020(C) - Pm25LD040(C) These seem to be the successors of the Pm25LV series. The main difference seems to be the dual I/O and additional erase opcodes. Some support an additional, complex locking register (maybe all of the above, but available datahsheets do not indicate it for all). The Pm25LD512C was tested by Chi Zhang: http://paste.flashrom.org/view.php?id=1579 Corresponding to flashrom svn r1671. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Atmel's AT25F series of SPI flash chipsStefan Tauner2012-12-291-0/+64
| | | | | | | | | | | | | | | | | | This adds support for the following chips: - AT25F512, AT25F512A, AT25F512B - AT25F1024, AT25F1024A - AT25F2048 - AT25F4096 Besides the definitions of the the chips in flashchips.c this includes - a dedicated probing method (probe_spi_at25f) - pretty printing methods (spi_prettyprint_status_register_at25f*), and - unlocking methods (spi_disable_blockprotect_at25f*) Corresponding to flashrom svn r1637. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel S33 series flash chipsStefan Tauner2012-12-291-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes: Bottom boot block: * 16Mb/2MB: QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8 * 32Mb/4MB: QB25F320S33B8, QH25F320S33B8 * 64Mb/8MB: QB25F640S33B8, QH25F640S33B8 Top boot block: * 16Mb/2MB: QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8 * 32Mb/4MB: QB25F320S33T8, QH25F320S33T8 * 64Mb/8MB: QB25F640S33T8, QH25F640S33T8 At least some seem to be marketed by other vendors (too?) but also with Intel's vendor ID. Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they support also erasing the top/bottom 8 8kB blocks with opcode 0x40. But since this command fails for all addresses outside those ranges, it is not easily implemented with flashrom's current code base and hence left out. Corresponding to flashrom svn r1636. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a generic SPI block unprotect functionStefan Tauner2012-12-291-109/+39
| | | | | | | | | | | This does not only remove a huge pile of duplicate code, it does also fix a bug in spi_disable_blockprotect_at25df(), which is also a good example why duplicated code is a bad idea. Corresponding to flashrom svn r1635. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Improve SPI status register pretty printingStefan Tauner2012-12-291-0/+591
- Move all functions related to SPI status registers to a new file spi25_statusreg.c. This includes the generic as well as the SST-specific functions from spi25.c and the chip-specific functions from a25.c and at25.c. - introduce helper functions * spi_prettyprint_status_register_hex() * spi_prettyprint_status_register_bpl() * spi_prettyprint_status_register_plain() Use the latter on every compatible flash chip that has no better printlock function set and get rid of the implicit pretty printing in the SPI probing functions. - remove * spi_prettyprint_status_register_common() * spi_prettyprint_status_register_amic_a25lq032() because it can be fully substituted with spi_prettyprint_status_register_amic_a25l032(). * spi_prettyprint_status_register() (old switch, no longer needed) - promote and export * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1(). * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2(). * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3(). - add #define TEST_BAD_REW and use it for a number of Atmel chips which had only TEST_BAD_READ set even though they dont have erasers or a write function set. Corresponding to flashrom svn r1634. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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