From 9ce498ebdc7a81c29ca3041478f16dcdc0835239 Mon Sep 17 00:00:00 2001 From: Jonathan Kollasch Date: Sat, 6 Aug 2011 12:45:21 +0000 Subject: Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Currently the same chipset enable is used for MCP51 (nForce 430). There have been reports of successful writes with its variations (e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to the new "unsupported chipset"-message we will get success reports in the case this patch does not break anything on the MCP51-based boards. See also: http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html http://patchwork.coreboot.org/patch/3176/ Corresponding to flashrom svn r1405. Signed-off-by: Jonathan Kollasch Acked-by: Joshua Roys Acked-by: Stefan Tauner --- chipset_enable.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'chipset_enable.c') diff --git a/chipset_enable.c b/chipset_enable.c index c6015f0c..97001a7e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -801,6 +801,12 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name) { uint8_t old, new; + pci_write_byte(dev, 0x92, 0x00); + if (pci_read_byte(dev, 0x92) != 0x00) { + msg_pinfo("Setting register 0x%x to 0x%x on %s failed " + "(WARNING ONLY).\n", 0x92, 0x00, name); + } + old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { -- cgit v1.2.3