From 703de983d8ccdb94232bf30cc6e64389741a0fef Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 21 Jan 2020 09:10:51 -0700 Subject: sb600spi: Add spireadmode Added spireadmode for >= Bolton. Do not override speed or read mode for >= Bolton if parameter not specified. Minor cleanup of sb600spi.c code. TEST=Manual: deploy on tremblye read flash using various parameters BUG=b:147665085,b:147666328 BRANCH=master Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff Signed-off-by: Rob Barnes Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Angel Pons --- flashrom.8.tmpl | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'flashrom.8.tmpl') diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index aa5bcd45..fde98c04 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -497,11 +497,29 @@ Support of individual frequencies depends on the generation of the chipset: .sp * SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz .sp +-The default is to use 16.5 MHz and disable Fast Reads. +.sp * SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz .sp +-The default is to use 16.5 MHz and disable Fast Reads. +.sp * Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them .sp -The default is to use 16.5 MHz and disable Fast Reads. +-The default is to use the frequency that is currently configured. +.sp +An optional +.B spireadmode +parameter specifies the read mode of the SPI bus where applicable (Bolton or later). +Syntax is +.sp +.B " flashrom \-p internal:spireadmode=mode" +.sp +where +.B mode +can be +.BR "'Normal\ (up\ to\ 33 MHz)'" ", " "'Normal\ (up\ to\ 66 MHz)'" ", " "'Dual\ IO\ (1-1-2)'" ", " "'Quad\ IO\ (1-1-4)'" ", " "'Dual\ IO\ (1-2-2)'" ", " "'Quad\ IO\ (1-4-4)'" ", or " "'Fast\ Read'" "." +.sp +The default is to use the read mode that is currently configured. .TP .B Intel chipsets .sp -- cgit v1.2.3