From 4095ed797f87c92b52e15d9f6fdc0b895c414cc9 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 20 Aug 2014 15:39:32 +0000 Subject: Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Corresponding to flashrom svn r1844. Signed-off-by: Duncan Laurie Signed-off-by: Martin Roth Signed-off-by: Stefan Tauner Tested-by: Marc Jones Tested-by: Stefan Tauner Tested-by: Thomas Reardon Tested-by: Wen Wang Acked-by: Marc Jones Acked-by: Stefan Tauner --- ich_descriptors.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'ich_descriptors.c') diff --git a/ich_descriptors.c b/ich_descriptors.c index b1e081f2..90f31503 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -139,6 +139,7 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: { uint8_t size_enc; @@ -180,6 +181,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: return freq_str[value]; @@ -820,6 +822,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: if (idx == 0) { -- cgit v1.2.3