From 125a328b4d8445f41c9fdde9e51c1b2bb40ad72e Mon Sep 17 00:00:00 2001
From: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Date: Sun, 24 Jul 2022 17:11:05 +0300
Subject: spi25_statusreg: support reading/writing configuration register

One more variation of registers.

This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.

Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 include/spi.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'include/spi.h')

diff --git a/include/spi.h b/include/spi.h
index c77866c4..505aecd0 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -177,6 +177,11 @@
 #define JEDEC_WRSCUR_OUTSIZE	0x01
 #define JEDEC_WRSCUR_INSIZE	0x00
 
+/* Read Configuration Register */
+#define JEDEC_RDCR		0x15
+#define JEDEC_RDCR_OUTSIZE	0x01
+#define JEDEC_RDCR_INSIZE	0x01
+
 /* Enter 4-byte Address Mode */
 #define JEDEC_ENTER_4_BYTE_ADDR_MODE	0xB7
 
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