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| author | Tim Ansell <tansell@google.com> | 2021-05-09 08:12:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-09 08:12:36 -0700 |
| commit | d2d7ad1531a5330877aa752b743b3629345b7592 (patch) | |
| tree | 8a47492d9e04fd39016afe0dfbdaa7b8d1058ca6 | |
| parent | b3ab09776c8dc31a71ca2c7fbcb4575219232d16 (diff) | |
| parent | 404fbec751cd60121965938f416e29bb5556cee3 (diff) | |
| download | fpga-interchange-schema-d2d7ad1531a5330877aa752b743b3629345b7592.tar.gz fpga-interchange-schema-d2d7ad1531a5330877aa752b743b3629345b7592.tar.bz2 fpga-interchange-schema-d2d7ad1531a5330877aa752b743b3629345b7592.zip | |
Merge pull request #51 from gatecat/clarify-site-pip-usage
docs: Clarify correct usage of site PIPs
| -rw-r--r-- | docs/device_resources.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/docs/device_resources.md b/docs/device_resources.md index a2671c5..323e177 100644 --- a/docs/device_resources.md +++ b/docs/device_resources.md @@ -242,6 +242,19 @@ entered via the site port corresponding to the site pin. The first site wire in the site will be the site wire attached to the output BEL pin of the site port. From there site routing continues per above. +It is important to note that site PIPs can only be used to access placed cells +inside that site. Site PIPs cannot be used as general route-thrus, to route +from site input to output. General route-thrus across entire sites should use +tile pseudo PIPs as described below - even if a site pin is being validly used +for one sink pin of a net that is located inside the site; site PIPs cannot +also be used to leave the site again to reach other sinks. + +LUT route-thrus, for example, might require both site PIPs and tile pseudo +PIPs. The site PIP would be used to route through the LUT in order to access +an associated flipflop input inside the site. The tile PIP would be used to +route across the entire site as part of the general, inter-tile, routing +problem. +  ### Tile Types and site types |