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| author | Tim Ansell <me@mith.ro> | 2021-04-13 12:56:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-13 12:56:23 -0700 |
| commit | 9179a269218f415f96dda96e1e5e85de401d68cd (patch) | |
| tree | 67d03f746639cc3374b6e295d24ece0e9499d573 /docs/index.rst | |
| parent | b16d955f43dd8f59fc714d506461d1d9f8a4a777 (diff) | |
| parent | d0fb39ddbdb5816c25870ca4db36985a70799a81 (diff) | |
| download | fpga-interchange-schema-9179a269218f415f96dda96e1e5e85de401d68cd.tar.gz fpga-interchange-schema-9179a269218f415f96dda96e1e5e85de401d68cd.tar.bz2 fpga-interchange-schema-9179a269218f415f96dda96e1e5e85de401d68cd.zip | |
Merge pull request #33 from mithro/main
Adding Sphinx documentation generation for the docs.
Diffstat (limited to 'docs/index.rst')
| -rw-r--r-- | docs/index.rst | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/docs/index.rst b/docs/index.rst new file mode 100644 index 0000000..d8dc21e --- /dev/null +++ b/docs/index.rst @@ -0,0 +1,18 @@ +Welcome to FPGA Interchange documentation! +========================================== + +.. toctree:: + :maxdepth: 2 + :caption: Contents: + + device_resources + bel_and_site_design + pseudo_cells + + +Indices and tables +================== + +* :ref:`genindex` +* :ref:`modindex` +* :ref:`search` |